PM604e.h include file
static char *PM604e_h_id = "%Z%%M% %I% %W% %G% %U%";
/*
* COMPONENT_NAME: (PMperfmon)
*
* FUNCTIONS: Performance Monitor Routines PM604e.h
*
* ORIGINS: 27
*
* (C) COPYRIGHT International Business Machines Corp. 1996
* All Rights Reserved
* Licensed Materials - Property of IBM
*
* Redistribution and use in source and binary forms are permitted
* provided that the above copyright notice and this paragraph are
* duplicated in all such forms and that any documentation,
* advertising materials, and other materials related to such
* distribution and use acknowledge that the software was developed
* by International Business Machines Corp. (IBM), 1995. The name
* of IBM may not be used to endorse or promote products derived
* from this software without specific prior written permission.
* No express or implied patent, trademark, or other intellectual
* property rights or licenses (except as permitted above)
* are granted hereunder.
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE
*/
#define PM_MAX_EVENT_604e_C1 32
#define PM_MAX_EVENT_604e_C2 32
#define PM_MAX_EVENT_604e_C3 31
#define PM_MAX_EVENT_604e_C4 31
int pm_events_604e_c1 [PM_MAX_EVENT_604e_C1] = {
/* Selection */
/* Value Event Counted */
PM_NOTHING, /* 0 = No events counted */
PM_CYC, /* 1 = Processor cycles */
PM_INST_CMPL, /* 2 = Instructions completed per cycle */
PM_TB_BIT_TRANS, /* 3 = Time Base bit transition */
PM_INST_DISP, /* 4 = Instructions dispatched */
PM_IC_MISS, /* 5 = Instructions cache misses */
/* speculative (Instruction cache line-fill */
PM_DTLB_MISS, /* 6 = dtlb misses (not speculative) */
PM_BR_MPRED, /* 7 = Branches incorrectly predicted */
PM_RESRV_RQ, /* 8 = Reservations requested */
PM_LD_MISS_EXCEED_L2, /* 9 = Load data cache misses that exceeded
* threshold with lateral L2 cache intervention */
PM_ST_MISS_EXCEED_L2, /* 10= Store data cache misses that exceeded
* threshold with lateral L2 cache intervention */
PM_MTSPRS_DISP, /* 11= MTSPR instructions dispatched */
PM_SYNC, /* 12= SYNC instructions completed */
PM_EIEIO, /* 13= EIEIO instructions completed */
PM_FXU_CMPL, /* 14= Integer instructions completed */
/* (No loads or stores) */
PM_FPU_CMPL, /* 15= Floating-point instructions completed
* (No loads or stores) */
PM_LS_EXEC, /* 16= LSU produced result without an exception
* condition */
PM_SFX1_FINISH, /* 17= SCIU1 unit produced a result (On 604e this
* includes add, substract, compare,
* rotate, shift, or logical instructions) */
PM_FPU_FINISH, /* 18= FPU produced result */
PM_LS_DISP, /* 19= Instructions dispatched to the LSU */
PM_SFX1_DISP, /* 20= Instructions dispatched to the SCIU1 unit */
PM_FPU_DISP, /* 21= Instructions dispatched to the FPU */
PM_SNOOP_RECV, /* 22= Snoop requests received */
PM_LD_MISS_EXCEED_NO_L2, /* 23= Load data cache misses that exceeded
* threshold without lateral L2 cache
* intervention */
PM_ST_MISS_EXCEED_NO_L2, /* 24= Store data cache misses that exceeded
* threshold without lateral L2 cache
* intervention */
PM_BRU_CRU_IDLE, /* 25= Number of cycles the branch unit and CR
* unit are both idle */
PM_SFX0_IDLE, /* 26= Number of cycles the SFX0 unit is idle */
PM_LSU_IDLE, /* 27= Number of cycles the LD/ST unit is idle */
PM_L2PIN_TRANS, /* 28= Number of time the L2_INT pin transitions
* from zero to one */
PM_UNALIGNED_LD, /* 29= Number of unaligned loads that are
* executed */
PM_LQ_ENTRIES, /* 30= Number of entries in load queue
* (added each cycle) */
PM_IABR_COP_ST /* 31= Number of instruction breakpoint hits with
* softstop enabled in the COP */
};
unsigned int pm_events_604e_c2 [PM_MAX_EVENT_604e_C2] = {
/* Selection */
/* Value Event Counted */
PM_NOTHING, /* 0 = No events counted */
PM_CYC, /* 1 = Processor cycles */
PM_INST_CMPL, /* 2 = Instructions completed per cycle */
PM_TB_BIT_TRANS, /* 3 = Time Base bit transition */
PM_INST_DISP, /* 4 = Instructions dispatched */
PM_LD_MISS_CYC, /* 5 = Cycles of load misses */
PM_DC_MISS, /* 6 = Data cache misses (data cache line fills) */
PM_ITLB_MISS, /* 7 = itlb misses */
PM_BR_CMPL, /* 8 = Branches completed */
PM_RESRV_CMPL, /* 9 = Reservations successfully obtained */
PM_MFSPR_DISP, /* 10= MFSPR dispatched */
PM_ICBI, /* 11= ICBI instructions completed */
PM_SYNCHRO_INST_CMPL,/* 12= Pipeline flushing operations
* (On 604e, includes SC, ISYNC, MTSPR[XER],
* floating point operations with divide by 0,
* invalid operation when the 604e is in precise
* mode, branch when MSR[BE] is set, and
* LSWX with XER=0 and SO set) */
PM_BR_FINISH, /* 13= Branch unit produced a result (branch or
* CR-logical instruction */
PM_SFX0_FINISH, /* 14= SCIU0 produced a result
* (On 604e, add, subtract, compare, rotate,
* shift, or logical instruction) */
PM_CFX_FINISH, /* 15= MCIU produced a result. On 604e,
* multiply/divide or SPR instruction) */
PM_BR_DISP, /* 16= Instructions dispatched to the branch unit */
PM_SFX0_DISP, /* 17= Instructions dispatched to the SCIU0 unit */
PM_LD_CMPL, /* 18= Loads completed
* (On 604e, includes all cache operations,
* TLBIE, TLBSYNC, SYNC, EIEIO, and ICBI)*/
PM_CFX_DISP, /* 19= Instructions dipatched to the MCIU */
PM_SNOOP_HIT, /* 20= Snoop hits occurred */
PM_EE_OFF, /* 21= Number of cycles the MSR(EE) bit is off */
PM_CFX_IDLE, /* 22= Number of cycles the CFX unit is idle */
PM_SFX1_IDLE, /* 23= Number of cycles the SFX1 unit is idle */
PM_FPU_IDLE, /* 24= Number of cycles the FP unit is idle */
PM_L2PIN_HIGH_CYC, /* 25= Number of cycles the L2_INT pin is high */
PM_4INST_DISP, /* 26= Number of time 4 instructions are dispatchd */
PM_3INST_DISP, /* 27= Number of time 3 instructions are dispatchd */
PM_2INST_DISP, /* 28= Number of time 2 instructions are dispatchd */
PM_1INST_DISP, /* 29= Number of time 1 instructions are dispatchd */
PM_UNALIGNED_ST, /* 30= Number of unaligned stores executed */
PM_SQ_ENTRIES /* 31= Number of entries in store queue (added each
* cycle) */
};
int pm_events_604e_c3 [PM_MAX_EVENT_604e_C3] = {
/* Selection */
/* Value Event Counted */
PM_NOTHING, /* 0 = No events counted */
PM_CYC, /* 1 = Processor cycles */
PM_INST_CMPL, /* 2 = Instructions completed per cycle */
PM_TB_BIT_TRANS, /* 3 = Time Base bit transition */
PM_INST_DISP, /* 4 = Instructions dispatched */
PM_LSU_WT_BUSY, /* 5 = Cycles the LD/ST unit is stalled
* due to BIU or cache busy */
PM_LSU_WT_SQ_FULL, /* 6 = Cycles the LD/ST unit is stalled
* due to store queue being filled */
PM_LSU_WT_NA_OP, /* 7 = Cycles the LD/ST unit is stalled. Due to
* operands not available in the reservation
* stations */
PM_INST_INTO_LQ, /* 8 = Instructions written into the load queue
* Double counts misaligned loads - event 8
* in PMC4 */
PM_CMPLU_WT_ST, /* 9 = Cycles completion unit stalled waiting on a
* store or sync instruction at top of the queue */
PM_CMPLU_WT_UNF_INST, /* 10= Cycles completion unit is
* stalled for an unfinished instruction */
PM_SC_INST, /* 11= System calls */
PM_BRU_WT, /* 12= Cycles the branch unit is waiting for its
* operand */
PM_DISP_FETCH_CORR,/* 13= Fetch corrections made at DISP stage */
PM_DPU_WT_IC_MISS, /* 14= Cycles DISP unit is stalled due to
* icache miss (no instructions) */
PM_DPU_WT_NO_REOR_ENT, /* 15= Cycles DISP unit is stalled due to
* no reorder buffer entry available */
PM_DPU_WT_NO_FPR, /* 16= Cycles DISP unit is stalled due to
* no FPR rename buffer available */
PM_INST_TABLEWALK, /* 17= Instruction table walks */
PM_DATA_TABLEWALK, /* 18= Data table walks */
PM_FPU_WT, /* 19= Cycles the FPU was stalled */
PM_SFX1_WT, /* 20= Cycles the SFX1 was stalled */
PM_BIU_FORW_NC_DATA, /* 21= BIU forwards non-critical data from the
* linefill buffer */
PM_DB_TRANS_1DEEP_PIPE, /* 22= Data bus transactions which finish with
* pipelining 1 deep */
PM_DB_TRANS_3DEEP_PIPE, /* 23= Data bus transactions which finish with
* pipelining 3 deep */
PM_BURSTRD_STREAM_FASTL2, /* 24= Burst reads which were streamed in
* fastl2 mode */
PM_WR_HIT_SHR_KILL_BRC, /* 25= Write-hit-on shared Kill broadcasts */
PM_ALL_CASTOUTS, /* 26= All castouts */
PM_2CASTOUT_BF, /* 27= Cycles exactly 2 castout buffers occupied */
PM_DC_ACC_RETR_CASTOUT_BUSY, /* 28= Dcache accesses retried due to
* castout buffers being busy */
PM_LD_MISS_DC_SHR, /* 29= Load miss linefills brought into the
* d-cache in a shared state */
PM_CRLU_PROD_RES /* 30= CR logical unit produced a result */
};
unsigned int pm_events_604e_c4 [PM_MAX_EVENT_604e_C4] = {
/* Selection */
/* Value Event Counted */
PM_NOTHING, /* 0 = No events counted */
PM_CYC, /* 1 = Processor cycles */
PM_INST_CMPL, /* 2 = Instructions completed per cycle */
PM_TB_BIT_TRANS, /* 3 = Time Base bit transition */
PM_INST_DISP, /* 4 = Instructions dispatched */
PM_LSU_WT_MMU_BUSY, /* 5 = Cycles the LD/ST unit is stalled
* due to MMU busy */
PM_LSU_WT_LQ_FULL, /* 6 = Cycles the LD/ST unit is stalled
* due to load queue being filled */
PM_LSU_WT_ADDR_COLL, /* 7 = Cycles the LD/ST unit is stalled
* due to address collisions */
PM_MISSAL_LDS_1PL2_AC, /* 8 = Misaligned loads that are cache hits for
* both the 1st and 2nd accesses - see event
* 8 in PMC3 */
PM_INST_INTO_SQ, /* 9 = Instructions written into the store queue */
PM_CMPLU_WT_LD, /* 10= Cycles completion unit is
* stalled for a load instruction */
PM_BTAC_HITS, /* 11= Number of hits in the BTAC */
PM_4BASIC_BLK, /* 12= Times the 4 basic blocks were used */
PM_DECOD_FETCH_CORR, /* 13= Fetch corrections made at decode state */
PM_DPU_WT_NO_UNIT, /* 14= Cycles DISP unit is stalled due to
* no unit available */
PM_DPU_WT_NO_GPR_RENAM, /* 15= Cycles DISP unit is stalled due to
* no GPR rename buffer available */
PM_DPU_WT_NO_CR_RENAM, /* 16= Cycles DISP unit is stalled due to
* no CR rename buffer available */
PM_DPU_WT_CNTRLNK_INTLK, /* 17= Cycles DISP unit is stalled due to
* counter-link interlock */
PM_INST_TABLEWALK_CYC, /* 18= Cycles doing instruction tablewalks */
PM_DATA_TABLEWALK_CYC, /* 19= Cycles doing data tablewalks */
PM_SFX0_WT, /* 20= Cycles the SFX0 was stalled */
PM_CFX_WT, /* 21= Cycles the CFX was stalled */
PM_BUSRQ_NOGRANT_BCYLES, /* 22= Bus cycles the processor has an internal
* bus request and dooes not have a
* qualified bus grant */
PM_DB_TRANS_2DEEP_PIPE, /* 23= Data bus transactions which finish with
* pipelining 2 deep */
PM_DB_TRANS_DBWO_REORD, /* 24= Data bus transations that use
* Data Bus Write Only reorder feature */
PM_ADDR_BUS_TRANS_ARTRY, /* 25= Processor address bus transactions that
* were ARTRY'd */
PM_SNOOP_PUSH_DED_BF, /* 26= Snoop pushes from the dedicated snoop
* push buffer */
PM_1CASTOUT_BF, /* 27= Cycles exactly 1 castout buffer occupied */
PM_3CASTOUT_BF, /* 28= Cycles exactly 3 castout buffers occupied */
PM_LD_MISS_DC_XU, /* 29= Load miss linefills brought into the d-cache
* in an Exclusive Unmodified (XU) state */
PM_INST_NOTDISP_AFTER_BR /* 30= Instructions not dispatched beyond
* branch */
};