CMS GOL Chip IMS Tester Card Design

CMS GOL TESTER CARD

The PPD Electronics Engineering Department is currently providing support for the development of the GOL ASIC that has been designed by CERN. We are currently designing a test card that will be used as part of production testing of the GOL chips. The printed circuit board has been designed to connect to the IMS tester that is used at CERN. The primary contact or liaison for the CMS GOL test card project in the EE Department is - Marcus Larwill

The following are some of the current design files for the CMS GOL test card projects:

ALL Gerbers in one file
(PDF versions zipped)

Gerber Etch top layer 1(PDF version)

Gerber Etch layer 2(PDF version)

Gerber Etch layer 3(PDF version) Showing +2.5V power plane

Gerber Etch layer 4(PDF version) Showing +3.3V power plane

Gerber Etch layer 5(PDF version) ground plane

Gerber Etch layer 6(PDF version) ground plane

Gerber Etch layer 7(PDF version)

Gerber Etch layer 8 bottom(PDF version)

Gerber paste bottom(PDF version)

Gerber paste top(PDF version)

Gerber silkscreen bottom(PDF version)

Gerber silkscreen top(PDF version)

Gerber solder mask bottom(PDF version)

Gerber solder mask top(PDF version)

combined Gerber top etch and mask(PDF version)

combined Gerber bottom etch and mask(PDF version)

combined Gerber of all Etch layers and Mask(PDF version)

ALL Schematics in one file
(PDF versions zipped)

Top Block Diagram (PDF version)

Schematic - Ims Connector Page1 (PDF version)

Schematic - Ims connector Page2 (PDF version)

Schematic - Glink (PDF version)

Schematic - TLK1501 (PDF version)

Schematic - TLK2501 (PDF version)

Schematic - RF switch (PDF version)

Schematic - Gol block (PDF version)

Schematic - Gol chip (PDF version)

Schematic - Optical interface (PDF version)

last modified 04/06/2004 Comments or Questions? larwill@fnal.gov


Security, Privacy, Legal