Drift Chamber FEE / DCM Data Formats
J.Nagle and C.Y. Chi created 4-30-98
updated 5-21-98
The following document is meant to review the data format for the Drift Chamber (DC) as:
(1) Output from the FEE to the DCM
Below is the format as sent from the DC FEE over fiber to the DCM. The data is sent in 20-bit words (with additional CAV and DAV control lines). The data packet is of fixed length at 972 words.
|
Sequence Number |
20-bit word format |
CAV |
DAV |
Comments |
|
1 |
0xFFFFF |
1 |
0 |
(all bits on handshake) |
|
2 |
0x00300 |
0 |
1 |
Detector ID |
|
3 |
Event Number |
0 |
1 |
16 bits L1 accept no. |
|
4 |
Module Address |
0 |
1 |
* DC specified |
|
5 |
Flag Word |
0 |
1 |
|
|
6 |
FEM Beam Clock Counter (8 bits) |
0 |
1 |
Least significant bits |
|
7 |
First Data Word (use full 20 bits) |
0 |
1 |
*see table below |
|
. . . |
. . . |
0 0 0 |
1 1 1 |
|
|
966 |
Last Data Word (use full 20 bits) |
0 |
1 |
|
|
967 |
User Word 1 |
0 |
1 |
Loaded from ARCNET |
|
968 |
User Word 2 |
0 |
1 |
Loaded from ARCNET |
|
969 |
User Word 3 |
0 |
1 |
Status word |
|
970 |
User Word 4 |
0 |
1 |
All zeros |
|
971 |
Longitudinal Parity Word |
0 |
1 |
|
|
972 |
0x00000 |
1 |
0 |
(all bits off handshake) |
The data words contains 48 samples (5-bits of information each) from each of 80 channels per FEM. The earliest time sample is placed in the least significant bit range.
|
Data Seq. |
DC Physical Channel Number |
Data Words |
|||
|
Bits 19-15 |
Bits 14-10 |
Bits 9-5 |
Bits 4-0 |
||
|
1 |
1 |
Sample 3 |
Sample 2 |
Sample 1 |
Sample 0 |
|
2 |
1 |
Sample 7 |
Sample 6 |
Sample 5 |
Sample 4 |
|
3 |
1 |
Sample 11 |
Sample 10 |
Sample 9 |
Sample 8 |
|
. . . |
. . . |
||||
|
12 |
1 |
Sample 47 |
Sample 46 |
Sample 45 |
Sample 44 |
|
13 |
41 |
Sample 3 |
Sample 2 |
Sample 1 |
Sample 0 |
|
. |
. |
||||
|
24 |
41 |
Sample 47 |
Sample 46 |
Sample 45 |
Sample 44 |
|
. |
|||||
|
2 |
|||||
|
. |
|||||
|
42 |
|||||
|
. |
|||||
|
3 |
|||||
|
. |
|||||
|
43 |
|||||
|
. |
|||||
|
. |
|||||
|
. |
. |
||||
|
960 |
80 |
Sample 47 |
Sample 46 |
Sample 45 |
Sample 44 |
Thus, there are 12 words for each channel and the channel order is 1, 41, 2, 42, 3, 43, 4, 44,…..39, 79, 40, 80. This output is from Boards 1,2 and is initiated when Endat[0] is set. The output is from Boards 3,4 when Endat[1] is set. The channel order is then 81, 121, 82, 122, …., 119, 159, 120, 160.
On Day-1 running, two FEM packets will be sent to the same DCM. In this case the DCM will receive two packets of 972 words each. Each set will have its own header and trailer words. They are clearly distinguished by the module address word in each packet header.
(2) (HIT FORMAT 403) Output from DCM in pass-through mode
If the DCM is in pass-through mode (no zero suppression), the data still passes through an FPGA and is reformatted before going into the on-board DSP. All data is transferred into the DSP in 32-bit words.
|
Sequence Number |
Bit 31 |
Bits 30-24 |
Bits 23-20 |
Bits 19-0 |
|
1 |
1 |
0 |
0 |
Detector # |
|
2 |
1 |
0 |
1 |
Event # |
|
3 |
1 |
0 |
2 |
Mod. # |
|
4 |
1 |
0 |
3 |
FLGS |
|
5 |
1 |
0 |
4 |
CLK Count |
|
1 |
0 |
0 |
0 |
Data 0 |
|
2 |
0 |
0 |
1 |
Data 1 |
|
3 |
0 |
0 |
2 |
Data 2 |
|
. . |
. . |
. . |
. . |
. . |
|
12 |
0 |
0 |
11 |
Data 11 |
|
13 |
0 |
1 |
0 |
Data 0 |
|
14 |
0 |
1 |
1 |
Data 1 |
|
. . . . . |
. . . |
. . . |
. . . |
. . . |
|
948 |
0 |
78 |
11 |
Data 11 |
|
949 |
0 |
79 |
0 |
Data 0 |
|
950 |
0 |
79 |
1 |
Data 1 |
|
. . |
. . |
. . |
. . |
. . |
|
960 |
0 |
79 |
11 |
Data 11 |
|
1 |
1 |
1 |
0 |
User Word 1 |
|
2 |
1 |
1 |
1 |
User Word 2 |
|
3 |
1 |
1 |
2 |
User Word 3 |
|
4 |
1 |
1 |
3 |
User Word 4 |
|
5 |
1 |
1 |
4 |
Parity Word |
|
6 |
1 |
127 |
15 |
Last Word |
The sequence numbers listed on the left column are not included in the data stream, just the 32-bit word sequence. In this mode, the number of words in the packet is of fixed length. The total packet length is = 5 + 960 + 6 = 971 32-bit words.
Bit 31 is zero for the raw data words and one for all others (header, user and trailer words). Bits 30-24 for the raw data words indicate the count number (0-79) and bits 23-20 indicate the data sequence (0-11).
The last word include some FPGA checking status, which we are not fully specifying yet.
Special Note è The count numbers coming out of the DCM in bits (30-24) count the numbers from 0 to 79 in sequence. This is easiest in the FPGA and allows for unique identification. If one wants to translate that into DC physical channel number the following applies.
If the packet is from Boards 1,2, then for even count numbers (0,2,4,…..,78) the DC physical channel number = (count number / 2) + 1. For odd count numbers (1,3,5,…..,79) the DC physical channel number = ((count number-1) / 2 ) + 41. If the packet is from Boards 3,4, then for even count numbers, the DC physical channel number = (count number / 2) + 81, and for odd count number, the DC physical channel number = ((count number-1) / 2) + 121.
With zero-suppression the data packet is no longer of fixed length. The format in each line is the same as above in format (2), except now some of the data words can be missing. Enough information is provided in the upper 12 bits to determine which words are which.
The zero-suppression method employed in the FPGA for DC is to check each incoming 20-bit data word (this does not include header words and user words) and if ALL 20 bits are equal to zero, then the word is removed from the output stream.