Ron Soltz (5/28/03):
Hi Sten,
The TPC in MIPP makes use of a gating grid, a wire plane with
alternating +/- voltages that sits directly above anode plane. It's purpose
is to terminate all field lines above the ground plane (and avalanche
region) to prevent charge build-up in the TPC when we don't want to read it
out. See the attached figure for an illustration of the grid itself.
A gating grid driver is used to turn the grid off quickly (of order 1
microsecond) when we want to read out an event. The previous gating grid
drivers gave out during the last experiment in which the TPC was used, and
we need to rebuild it.
We have obtained the
plans
for a similar device used for the STAR Experiment TPC,
which we have posted. This device is more
complicated than what we need, but Peter helped me to dissect it, and we
feel that some parts of the module can be built directly from this diagram.
For example the upper right corner appears to be a digital voltage control,
but we have many fewer channels to operate than STAR (2 vs. 128), and we
can do without any software controls.
The basic requirements are
1. Adjustable voltage bias, from 0 to +200V (can be an external pot)
2. Adjustable difference voltage for two channels (0 to +/-200V)
3. Input/Output
We require the following inputs:
Input-1 BNC enable
Input-2 BNC trigger gate (to turn off grid)
We require high and low voltage outputs for two channels:
Chan-1 High Voltage
Chan-1 Low Voltage
Chan-2 High Voltage
Chan-2 Low Voltage
The two channels are for the front and back halves of the TPC.
These channels do not need to be set independently.
Finally, can you help us to build this module? We will also need one
spare, although additional channels on the same module may also serve this
function. We recommend working from the existing STAR schematic is meant to
save time. If it you find other ways to achieve the voltage switching we
need, let us know. Please include Peter Barnes in any correspondence, as he
is working working with me on this.
Sten Hansen (5/29/03):
I think we can build a driver. The Schematic in the URL listed in
your message seems very complicated. I don't see any digital control of
the voltages. Perhaps I not looking at the same schematic. The one on the
web page has what appears to be 2 inverters to generate the + and - 200V.
There are pots that control pass FETs which I assume set the voltage.
It seems very complicated. There are 8 isolated amplifiers, Three
isolated low voltage supplies plus the two bias generators.
We have recently made a PMT gate which switches a dynode 300v to kill
its gain. We just used an off the shelf low side/high side driver (see:
http://www.irf.com/product-info/datasheets/data/ir2101.pdf),
plus the two HV Fets which in our case come two to an SO-8 package. (see:
http://www.fairchildsemi.com/ds/FQ/FQS4903.pdf)
Since our load capacitance is <50pF it switches in something like 50ns.
What is the electrode capacity of the grid and what is the duration of
your gating pulse? I assume the steady state currents required are in the
uA range. We are making cokroft-walton PMT bases. A section or
two of that I should think could generate the 200v, or we could use the
generator section shown in the schematic.
The one thing I don't know anything about is the transformer used at the
output. It appears to perform as some sort of damping/pulse shaping/load
balancing function. Presumably we can copy that verbatum, unless
theelectrical properties of your grids differ from the Star TPC.
Peter Barnes (5/30/03):
At the end of our discussion today I owed you some information:
1. GG DC Power Supply Schematic:
Should be very similar to this
annotated
copy of the ALEPH GG PS.
This appears to show that the supply voltage limits are
GG Power Supply Signals, Controls, and Limits
| Signal |
GG Power Supply Control Name |
Limits |
| VGG |
"Offset" |
-100 V |
| VGGH |
"Positive" |
+150 V |
| VGGL |
"Negative" |
-150 V |
The front panel BNC monitors are divided by 100. The box can also
supply +5 V to the gating module, if that helps.
2. GG Operating Voltages:
We have
selected
logbook pages from Brookhaven E895,
the last experiment to use the TPC.
In particular,
p. 155 quotes 0.02 muF as the chamber capacitance, used there for
testing the GG drivers.
p. 13 quotes voltages of Vgg = 80 V, Vggh = 180 V, Vggl = 20 V.
p. 15 shows some waveforms, 20 mus on time.
p. 17 shows 22 mus on time, 500 ns rise time, and more waveforms.
p. 18 also quotes 0.02 muF
3. GG Wire Size and Spacing
I haven't found this in any of our documentation. I'll ask Gulshan
Rai (one of the original builders).
4. I'll also ask Fred Bieser about the output transformer.
Peter Barnes (6/6/03):
Hello Fred [Bieser],
We have been making steady progress in preparing the EOS TPC for
installation in E907 at Fermilab. I have a few questions for you:
First, in the process we took a long look at all the connections, and
there are two we can't decipher. These are the most downstream SHV
connector on each side. These appear to connect to the bottom of the Kapton
strip which has the anode/field wires glued on top. You can see this
connection
here, look at
P5304773.jpg
Any hints?
Second, we have decided to build new gating grid drivers, since STAR
doesn't have enough to share. They use a transformer on the output for some
sort of damping/pulse shaping/load balancing function. We've got their
schematic
here.
Do you remember anything about this?
Fred Bieser (6/9/03):
I can't really see anything from the thumbnail; you should ask Howard
Wieman as this was his baby.
You should ask the 'father' of the STAR gated grid pulsers: Vahe
Ghazikhanian vahe@physics.ucla.edu It is a 'bifilar' transformer to help
match the differential signals to minimize charge injection into the
preamps. I should warn you that I have found the ripple from his DC-to-DC
HV power supplies make too much noise on the anode wires (but seem to do no
harm to the pad signals.) You probably don't care about the anodes (?) but
in STAR we use them for fast triggering.
Peter Barnes (06/09/04):
The pictures are now up. The mystery connection is the purple wire in
this picture.
Also, there is a mystery block on the beam right side of
the field cage ground flange:
this picture. Any memories?
Thanks for the ripple warning. We haven't decided yet
whether to replace the analog supplies we have from EOS days
with something like the STAR converters.
Sten Hansen (7/3/03):
Erich and I went out this afternoon with a twinax to bnc dongle
for the capacitance meter. We measured 6.4 nF on the front connector which
matches the number we got yesterday with the clip leads. We still couldn't
get a connection at the side connector. It seems as if the center portion
of the twinax connector is loose. Are you planning to roll the TPC out
soon or should we try and look at the interior bore of the connector with
a dental mirror?
Xinyi Chen (7/15/03):
We have built a prototype of Gating Grid Driver.
In this prototype, two
PMT gate-able base boards are implemented to switch the VGGH(+150V) and
VGGL(-150V) on and off. The PMT gate board just used a High and Low side
driver chip to drive two power MOSFETs which operates up to 600 volts. In
order to meet the needs of gating grid driver, some small modifications
have been made to the PMT gate board. The attached PDF file is the
schematic of the prototype [ggdriver_01.pdf,
.gif]. There are two inputs in the unit:
Enable and Gate Trigger. Both of them are TTL level and High active. As a
high voltage power source, the GG DC Power Supply is used to provide
appropriate DC power to the unit.
In the testing, the Gating Trigger Pulse that used to control VGGH and
VGGL outputs has the width of 25 us. During the Gating Trigger Pulse is
active; the output voltage swings between -150V to +150V. The test results
shown that the outputs with 680pf capacitance load to ground are very good.
See the attached waveforms
[ggdriver_v1_out.jpg,
.tif]; for detail.
Please come here to take a look how the prototype works and give us your
comments. We will make some changes if necessary and then continue this
job.
I also want to know what is the input gating signal level you need: TTL or NIM?
Peter Barnes (7/25/03):
Thanks for showing me your prototype and discussing what to do next.
I just wanted to write down the decisions we made, and I have a question
about the pulse length:
- The final board will be installed directly inside the GG DC PS chassis.
- We have 3 of these chassis, (2 operational, 1 spare). We should
probably make 4 boards.
- The input logic levels (ENABLE, GATE) will be TTL.
- The active state will be both outputs (VGGH_OUT, VGGL_OUT) at the
common offset voltage (VOFF). The quiescent state will be
VGGH_OUT = VGH_IN+, VGGL_OUT = VGL_IN-. This is
the reverse of your prototype.
- The common mode potentiometer around the output transformer will
be screw-driver adjustable from the front panel.
- The output circuit will include a header (or equivalent) for us
to add output impedance and slow down the rise time.
- The output will pass through a DPDT front panel switch, which
select either the triggered output or both outputs at the active
state, VOFF. The switch positions should be labeled "TRIGGERED"
and "TRANSPARENT".
- Monitors for both outputs will be on the front panel. These
monitor outputs will use 100:1 dividers (5K:50 ohm). These monitors
will be taken after the DPDT switch.
Questions:
- I've forgotten what sets the pulse length. Is it the GATE width?
or hardwired? If hardwired, we'll have to get you a good number, and
put the relevant components on a header (or use a pot), so we can make
adjustments later.
- You and Sten also discussed the common mode capacitance? I don't
recall exactly what this was about.
Xinyi Chen (7/30/03):
The attached documents are up to date GG Driver schematic
[pdf]
and testing waveforms [ggdriver_v2_out1.jpg,
ggdriver_v2_out2.jpg].
I would like to talk to you something about the GG driver.
- Some modifications have been made to the prototype. Both outputs
will be in the ACTIVE states
(VGGH_OUT = VOFF- = VGGL_OUT) when the GATE_IN is
active only (TTL high level); otherwise they always stay in the
GUIESCENT states (VGGH_OUT = VGH_IN+,
VGGL_OUT = VGL_IN-). See the attached waveforms for
detail.
- The switch S1 is added to select both outputs to be triggered or
not. When the switch is turned to the NO TRIGGER position, both
VGGH_OUT and VGGL_OUT will be connected to VOFF through two 100K
resistors respectively. This switch will be located on the front
panel.
- The zero ohm resistors R21 to R24 can be used to add output
impedance by changing their values.
- If the 5K:50 ohm dividers are implemented to the output monitors,
the 5050 ohm resistance will take an additional 5 watts power (30 ma)
from VGGH_OUT and VGGL_OUT. To reduce the additional power
consumptions, they are replaced with the 51K:510 ohm dividers. This
will result in that the 100:1 divider will change to 1000:1 divider
when the monitor outputs terminated with 51 ohm resistors such as a
oscilloscope with the 51 ohm input impedance is connected. Both monitor
outputs will use BNC connectors and be located on the front panel.
- For the purpose of testing, a simple pulse generator has been made
to simulate the Gate Trigger signal. The width of the pulse is
adjustable from 5 us to 50 us and it triggered by an external function
generator. This pulse generator is not shown in the schematic.
Peter Barnes (7/30/03):
Thanks for sending along this information. Appart from mounting
details, it looks like you have made all the changes we talked about.
Looking at the schematic, I have a few questions:
- The VGL_MONIT output is mis-labeled.
- I can't figure out why the VGH_MONIT circuit is different
from VGL_MONIT. It looks like VGH_MONIT reads 10 V low, because
of Zener D4. Why is C8 needed? Should the equivalent be on VGL_MONIT?
- What is the purpose of R25?
- On the output monitor dividers, why stop at 51K? The input monitors
use 1M, which would give 10 mW, instead of 200 mW.
- We should remember to label all the monitor outputs as high impedance,
so we don't get confused by trying to use 50 ohm scope inputs.
- The input trigger pulse width sets the output pulse width, correct?
Xinyi Chen (8/1/03):
Here are the answers about your questions
[ggdriver_v3.pdf]:
- The VGL_MONIT output is mis-labeled; I will collect it.
- In the applications of HV Floating MOS-Gate Driver ICs such as
IR2101, the Gate voltage must be 10-15V higher than the Drain voltage
in order to drive the HV power MOSFET in full enhancement. Being a high
side switch, such gate voltage would be the highest voltage in the
system. In the GG driver prototype, the zener diode D10 is added to
meet this requirement for VGGH side. In the VGGL side, D1 and D2 are
utilized to instead an extra zener diode. If this is not met, the HV
output will have a small voltage drop (approximate 10V) when the MOSFET
is driven for long time (more than 50ms). The attached waveforms
[ggdriver_v3_out.tif]
shown the case without D10 and the voltage drop appeared at 67.6ms
later since triggered. In fact, the real VGGH_IN is +160V to get the
+150V Drain voltage for Q1. That's why the VGH_MONIT is connected to
the Drain of Q1. The Drain voltage of Q1 is used as a DC Power source
for the VGGH_OUT; the C8 is a bypass capacitor.
- The R25 existed already in the Aleph Gating DC Power System (R15).
I think this resistor is just as a load.
- If you do not use any monitor equipment with 50 ohm input
impedance, the output monitor dividers will use 1M to instead 51K.
- The input trigger pulse width sets the output pulse width; this is
correct.
Sten Hansen (10/20/03):
Hello Joyce:
We would like to make 4 cards of the Gerbers that are attached. The
material would be .093" FR4. The cards are 2.5" x 5.5", four layers. Could
we get a price for 10 and 15 day delivery?
We would like to send the latest version of the files to you before you
begin production.
Joyce Cabello (10/20/03):
Dear Sten,
Thank you for the opportunity to submit Quotation #031020-003 attached.
[Gating_Grid_Quotation.doc]
Have a good day,
Joyce Cabello
Cordova Printed Circuits, Inc.
408-942-1100 Phone
408-946-3252 Fax
joyce.cabello@cordovaprintedcircuits.com
or cordova1@ix.netcom.com
www.cordovaprintedcircuits.com
