Relative and absolute jitter measurements have been made on key components of the PHENIX timing system and are presented herein. The jitter measurement which is of most interest to the sub system developers is the relative timing jitter between FEMs in one granule. This was measured to be on the order of 40 ps full with at half max and 260 ps peak to peak.

Two types of jitter measurements were performed. One being an absolute jitter measurement and the other a relative one. An absolute jitter measurements is a measure of the clock jitter relative to its source at various points along a path which the clock travels as it is affected by various electronic components. A relative clock jitter measurement is one in which the clock has been fanned out and the jitter measurement is made relative to one of the fanout components. See figure 1 for a diagram which should help resolve confusion.

Figure 1
Connect-o-grams showing the difference between an absolute and relative jitter timing measurement. The absolute measurement helps one understand how the clock jitter deteriorates as it moves from source to destination. The relative measurements helps one understand the effects of fanout junctions in the clock distribution system.

Diagrams of the different setups of the clock distribution system can be found in figures 2, 3 and 4. These different setups were used in order to simulate the various clock distribution configurations which will be present in the final PHENIX timing system. To describe the general setup in words, a WaveTek pulse generator was used to generate a 10MHz clock, using its TTL trigger output. This signal was converted to a differential ECL signal and plugged into the MTM transition card. The MTM fans out the clock to two GTMs. The GTMs are used to drive the mode bits and clock signal to the GTSTM modules through one or two GFMs, depending on the current jitter measurement being made.

The clock distribution setup from the external WaveTek pulser to the GTMs was constant through out these jitter measurements. Due to the lack of GTSTMs and GFMs, several setups down stream of the GTMs were needed in order to perform all the jitter measurements of interest. For the absolute jitter measurements, only one GTSTM was used which was hooked up to one GTM through one and then two GFMs.

For the relative jitter measurements simulating FEMs in two separate granules, the clock was probed at the front panel output of the two GTMs as well as the output on the two GTSTM. Since there are only two GFMs available, each mode bit signal was fanned out only once.

Again, figures 2, 3 and 4 have diagrams of the exact setup of timing system components and at which point the clock was being probed.

The resulting absolute jitter measurements are tabulated in table 1. Click on the Raw Data hyper-link to view the jitter-grams measured by the Tektronics Communication Analyzer (CA).

Table 1
Absolute jitter measurements taken at various points along the PHENIX timing distribution path.

Connect-o-gram Ref. Figure #2	Probe Point	Reference Color on figure 2	Jitter FWHM in pico sec	Jitter Peak to Peak in pico sec	Raw Data Hyper Link
	TTL to ECL	Blue	2.746	18.4	Raw Data
	GTM Front Panel, x1 Beam Clock	Red	60.73	432	Raw Data
	GTM Front Panel, x4 Beam Clock	Green	57.89	442	Raw Data
	Glink Tester, 1 VFM	Yellow	65.9	464	Raw Data
	Glink Tester, 2 VFM	Yuck Brown	69.9	446	Raw Data

Figure 3
Diagrams showing how two of the relative jitter measurements were taken. Click on the Raw Data hyper-links to view jpeg files of the jitter distributions.

Relative jitter measured between two FEMs in one granule.	Relative jitter measured between two GTMs.
Jitter: 41.52ps FWHM, 262 PkPk	Jitter: 140.6 ps FWHM, 964 PkPk
Raw Data WO Atten. Raw Data W Atten.	Raw Data

Figure 4
Another diagram showing how the relative jitter measurement was taken simulating two FEMs in different granules. Click on the Raw Data hyper-links to view jpeg files of the jitter distributions.

Relative jitter between FEMs in two different granules
Jitter: 75.99ps FWHM, 492ps PkPk
Raw Data

In conclusion, the absolute jitter of the clock degraded to 70ps FWHM, 446ps PTP, as measured at the output of the GTSTM after the mode bit/clock had been fanned out twice via two GFMs. The MTM and GTM have delay circuitry which will enlarge the jitter by a yet unknown amount. This jitter measurement should be regarded as a lower bound measurement. It can be maintained if one resorts to using cable length trimming methods between the MTM and GTM modules. See the clock quality appendix for further details.

The FEM to FEM relative jitter measurement simulating FEMs in the same granule was measured to be 41.52ps FWHM and 262ps PTP. This includes a double fanout of the mode bit/clock signal via two GFMs which is the expected setup for the final PHENIX timing system configuration. An additional jitter measurement was made with the fiber cable connecting the first GFM to the second one replaced by one with a 5db attenuator. The additional jitter measured by introducing this 5db attenuator is about 1 ps and should be considered to be "in the noise".

The relative clock jitter between two granules was measured to be 75.99ps FWHM and 492ps PTP. This was measured using the two clock edges at the output of two GTSTM, each being driven by its own GTM and using a single GFM module. Since the final timing system will include two GFMs to distribute the mode bits/clock signal, one should expect this value to edge up by about 10%.

When the first attempt at making these jitter measurements was done, a problem arose causing the GTSTM to "lose lock". There is a phase lock loop circuit at the driving and receiving ends of the glink line. In some circumstances, the phase lock loop circuit on the receiving end of the glink line, could not stay locked onto the 800MHz clock it was receiving from the glink transmitting unit. This condition is referred to as "losing lock". When this occurs, no data is transmitted over the Glink line. The GTSTM would tend to loose lock under certain clock distribution setups. At the time, a LeCroy pulse generator was used to generate the external 10MHz clock and a GTM transition fanout card was being used to fanout the mode bit/clock data to the GTSTM. With this setup as well as when the external LeCroy clock was replaced by the internal MTM clock, the GTSTM would consistently loose its Glink lock within a few seconds after performing a Glink reset. (A Glink reset is a method by which one synchronizes the transmitting and receiving ends of the Glink line.)

After some analysis of the clock signal, several discoveries were made. The quality of the clock plays an important role in the ability for the Glink lines to remain locked. The LeCroy pulse generated had a relatively noisy clock. The internal MTM oscillator divide down circuit added an oscillatory jitter component which caused the Glinks to lose lock. Finally, the GTM transition card fanout unit was especially sensitive to the quality of the clock, thus aggravating the loss of lock problem.

A simple technique was used to measure the quality of the clock used to drive the timing system. The clock output was split in two using a power splitter. One copy of the clock was used to trigger the communication analyzer (CA) and second copy was delayed by about 30 ns and fed into the sampling input of the CA. The jitter was then measured at various points in time relative to the trigger. The further the measured clock edge was from the triggered one, the greater the jitter, as would be expected. The amount by which the jitter increased (i.e. the FWHM of the jitter distribution) as a function of the time from the triggered edge, was a good measure of the quality of the clock source. As an example, refer to figure 5. This figure contains two plots of the jitter as a function of time from triggered edge. The lower plot is that of the WaveTek pulse generator, and the upper plot is that from the LeCroy pulse generator. It is clear from this plot that the LeCroy pulse generator has about 10 times as much "jitter" as that of the WaveTek.

Figure 5
Clock quality plots comparing the WaveTek pulse generator to the LeCroy pulse generator. Notice the factor of 10 worse performance of the LeCroy pulse generator as one compares the clock jitter as a function of time distance from the triggered edge. The left graph plots the jitter as measured by the full width at half max of the jitter distribution and the right graph plots the peak to peak measure of the same jitter distribution.

A similar jitter distribution plot of the internal MTM clock measured at 4 us reviled a bifurcated plot, signature of an oscillatory jitter component present in the clock. It was later determined to be caused by two uncoupled divide down circuits in the MTM.

Figure 6
Bifurcated jitter distribution measured by the CA on the MTM internal clock. It has been hypothesized that this bifurcation is due to the design of the clock divide-down circuit. There are two independent divide down circuits causing a "beating" effect resulting in the bifurcation.

Finally, the GTM secondary fanout transition card was determined to be deficient due to the marginal capability of the clock fanout unit used to fanout the 800MHz signal to 5 Glink optical transmitters. The clock fanout was rated to run at 1GHz. Taking into account the rising and falling edge times of the signal going through the fanout circuit, which is on the order of .5 ns, and the 800MHz signal being fanned out, leaves little room for a jittery clock. Therefore a new fanout system was designed around a new, 2GHz 1 to 9 fanout circuit which is referred to as the GFM in the above text. This unit was able to keep the Glink locked under the same conditions which would cause the GTM transition card secondary fanout unit to lose lock.

To conclude this appendix section, the jitter measurements were made with the WaveTek pulse generator, and the GTM transition secondary fanout units were replaced by the new GFMs. With the clock quality issues being established as critical to the fanout of the clock through the Glink system, special attention is being paid to a new phase lock loop circuit. This new phase lock loop circuit is to be added to the MTM board for the purpose of cleaning up the clock jitter from the official RHIC clock, provided by the RHIC controls group. The "quality" of the RHIC clock is yet to be measured but plans are in place to fully characterize it.