From:    Marzio Pedrali-Noy, Lawrence Berkeley National Lab,
         MPedrali-Noy@lbl.gov
              Atul Joshi,         Lawrence Berkeley National Lab,
         Atul_Joshi@lbl.gov

To:      PEM Group

Subject: WTA3-IC: a 16 channel chip featuring the Track-and-Hold,
                  Winner-Take-All stage and the full logic of the PET Readout IC

Contents:
          Project presentation
          Bond pad list
          Pads description
          Test steps analog section
          Error logic
          Digital test pads
          Hspice final simulations

    This is the documentation on WTA3, a 16-channel chip containig the  Track-and-Hold, Winner-Take-All (WTA) and logical functions of the PET Readout Integrated Circuit (IC). The circuit was submitted to MOSIS on Dec. 11, for fabrication using HP's 0.5um, 3-metal CMOS process. The delivery date is estimated to be March 11, 1999. For updated status and scheduling informations concering the WTA3 run please visit the URL  http://www.mosis.org/cgi-bin/runstatus/calendar99_run_status/91x.sts .   This documentation does not cover the design and specification details of the IC, rather, it is intended to be a "user's reference".

        A block diagram of WTA3 is shown in   figure 1 .The Control Logic decodes the I2C protocol, controls the multiplexers, enables/disables individual input channels. Each channel consists of sample and hold capacitor,  WTA cell, local buffer and multipexer. The analog input of the winner channel is buffered out by the output buffer.

        The chip outline is shown in   figure 2 . The utilized die area is 3.07 mm x 3.85 mm . Bonding pads are 150 um x 90 um; input pads (left side) are on a 180 um pitch; channel output pads (right side) are  on a 180 um pitch on two rows staggered of 240 um; digital inputs/outputs (top) and analog inputs/outputs (bottom) are on a 130 um pitch. Close to the top there is a 4x8 matrix of 40 um x 40 um test probe pads for the digital section ; those pads are for monitoring purpose only and should not be bonded out. The test signal names and location are presented in table 2  .

        The values of the seven external power supplies necessary to operate the chip are shown on  table 1 .

  Figure 1. Block diagram of the 16-channel WTA3 chip

• BOND PAD LIST (counterclock wise from top left corner)

 pad schematic (ps format)
 

PIN# NAME                     FUNCTION                 VOLTAGE/CURRENT

   WTAIN<15>         Input channel 15     -1.65[V]dc + positive swing
    WTAIN<14>         Input channel 14     -1.65[V]dc + positive swing
    WTAIN<13>         Input channel 13     -1.65[V]dc + positive swing
    WTAIN<12>        Input channel 12     -1.65[V]dc + positive swing
    WTAIN<11>         Input channel 11     -1.65[V]dc + positive swing
    WTAIN<10>         Input channel 10     -1.65[V]dc + positive swing
    WTAIN<9>          Input channel 9      -1.65[V]dc + positive swing
    WTAIN<8>          Input channel 8      -1.65[V]dc + positive swing
    WTAIN<7>          Inut channel 7       -1.65[V]dc + positive swing
    WTAIN<6>          Input channel 6      -1.65[V]dc + positive swing
    WTAIN<5>          Input channel 5      -1.65[V]dc + positive swing
    WTAIN<4>          Input channel 4      -1.65[V]dc + positive swing
    WTAIN<3>          Input channel 3      -1.65[V]dc + positive swing
    WTAIN<2>          Input channel 2      -1.65[V]dc + positive swing
    WTAIN<1>          Input channel 1      -1.65[V]dc + positive swing
    WTAIN<0>          Input channel 0      -1.65[V]dc + positive swing
    CHIP_ADD<3>       Chip adress 3        external 0[V](=TRUE) or -3.3[V](=FALSE)
    CHIP_ADD<4>       Chip adress 4        external 0[V](=TRUE) or -3.3[V](=FALSE)
    VDDA!             Analog supply        external 0[V]
    VSSA!             Analog supply        external -3.3[V]
    IBIASWTA          Internal node        -0.91[V]
    VDC_I             Internal node        -1.35[V]
    VDC               Internal node        -2.25[V]
    COM               Internal node        function of input signal
    IFIGHT            Current supply       15uA
    IMASTER           Current supply       10uA
    I_OUTAMP          Internal node        -1.21[V]
    VN                Internal node        -2.42[V]
    I_LBUF            Internal node        -2.37[V]
    I_OUTBUF          Internal node        -2.27[V]
    I_OUTDRIVER       Internal node        -1.78[V]
    ANALOGOUT         buffered analog out
    GND!         substrate node external   -3.3[V]
    OUTCOMM           Internal node        -2.21[V]
    CHIP_ADD<1>     Chip adress 1          external 0[V](=TRUE) or -3.3[V](=FALSE)
    CHIP_ADD<2>     Chip adress 2          external 0[V](=TRUE) or -3.3[V](=FALSE)
    TOUTB            Internal node         -1.98[V]
    TOUT             Internal node         -0.82[V]
    OUTB<0>          Neg. output channel 0  0[V](=TRUE) or -3.3[V](=FALSE)
    OUT<0>           Pos. Output channel 0  0[V](=TRUE) or -3.3[V](=FALSE)
    OUTB<1>          Neg. output channel 1  0[V] or -3.3[V]
    OUT<1>           Pos. Output channel 1  0[V] or -3.3[V]
    OUTB<2>          Neg. output channel 2  0[V] or -3.3[V]
    OUT<2>           Pos. output channel 2  0[V] or -3.3[V]
    OUTB<3>          Neg. Output channel 3  0[V] or -3.3[V]
    OUT<3>          Pos. Output channel 3  0[V] or -3.3[V]
    OUTB<4>          Neg. output channel 4  0[V] or -3.3[V]
    OUT<4>           Pos. Output channel 4  0[V] or -3.3[V]
    OUTB<5>          Neg. output channel 5  0[V] or -3.3[V]
    OUT<5>           Pos. Output channel 5  0[V] or -3.3[V]
    OUTB<6>          Neg. output channel 6  0[V] or -3.3[V]
    OUT<6>           Pos. Output channel 6  0[V] or -3.3[V]
    OUTB<7>          Neg. output channel 7  0[V] or -3.3[V]
    OUT<7>           Pos. Output channel 7  0[V] or -3.3[V]
    OUTB<8>          Neg. output channel 8  0[V] or -3.3[V]
    OUT<8>           Pos. Output channel 8  0[V] or -3.3[V]
    OUTB<9>          Neg. output channel 9  0[V] or -3.3[V]
    OUT<9>           Pos. Output channel 9  0[V] or -3.3[V]
    OUTB<10>         Neg. output channel 10 0[V] or -3.3[V]
    OUT<10>          Pos. Output channel 10 0[V] or -3.3[V]
    OUTB<11>         Neg. output channel 11 0[V] or -3.3[V]
    OUT<11>          Pos. Output channel 11 0[V] or -3.3[V]
    OUTB<12>         Neg. output channel 12 0[V] or -3.3[V]
    OUT<12>          Pos. Output channel 12 0[V] or -3.3[V]
    OUTB<13>         Neg. output channel 13 0[V] or -3.3[V]
    OUT<13>          Pos. Output channel 13 0[V] or -3.3[V]
    OUTB<14>         Neg. output channel 14 0[V] or -3.3[V]
    OUT<14>          Pos. Output channel 14 0[V] or -3.3[V]
    OUTB<15>         Neg. output channel 15 0[V] or -3.3[V]
    OUT<15>          Pos. Output channel 15 0[V] or -3.3[V]
    VDD!             Digital supply         0[V]
    VSSD!            Digital supply         -3.3[V]
    ENA_BIT          external enable bit
    ENA_BITB         external neg. enable bit
    ERROR_BIT        error bit              0[uA](=FALSE) or 200[uA](=TRUE)
    BIT<0>           channel adress bit 0   0[uA](=FALSE) or 200[uA (=TRUE)
    BIT<1>           channel adress bit 1   0[uA] or 200[uA]
    BIT<2>           channel adress bit 2   0[uA] or 200[uA]
    BIT<3>           channel adress bit 3   0[uA] or 200[uA]
    SDOUT            serial data out        0[uA] or 200[uA]
    RST              external reset bit
    RSTB             neg. external reset bit
    SDA              external serial data in
    SDAB neg.        external serial data in
    SCL              external serial clock in
    SCLB             neg. external serial clock in
    SH               external sample/hold
    SHB              neg. external sample/hold
 
 
 
 
 
 

CONVENTIONS

vdda! most positive analog supply
vssa! most negative analog supply
vdd!  most positive digital supply
vssd! most negative digital supply
gnd!  psubstrate supply

padname (R) required bonding
padname (T) test pad
 

• PADS DESCRIPTION

ifight (R) Input external current source, is the current the channels fight for.
a trimpot between pad and vdda! can be used.

imaster (R) Master external current reference; a trimpot
between pad and vssa! can be used.

Currents in the chip are ratioed as follows:

master : comparator = 1 : 1
master : inputwta = 1 : 1
master : localbuffer = 2 : 3
master : outbuffer = 1 : 3
master : outampli = 1 : 3
master : outdriverbias = 1 : 24
outdriverbias : outdriver = 1 : 5
( master : outdriver = 1 : 120 )
 
 

comm (T) current summing node of the wta channels;
allows multiple wta chip connection.

vdci (T) internal voltage reference, nominally at the
middle of power supplies.

vdc (T) internal voltage reference, input circuit wta

ibiaswta (T) internal voltage reference, input circuit wta

i_outamp (T) internal voltage reference,
a trimpot between pad and vssa! can be used
to increase the current in outampli;
injected extra current : outampli = 1 : 3

vn (T) internal voltage reference,
a trimpot between pad and vdda! can be used to
increase the current in comparator;
injected extra current : comparator = 1 : 1

i_lbuf (T) internal voltage reference,
a trimpot between pad and vdda! can be used
to increase the current in local buffer;
injected extra current : local buffer = 1 : 1

i_outbuf (T) internal voltage reference,
a trimpot between pad and vdda! can be used
to increase the current in outbuffer;
injected extra current : outbuffer = 1 : 1

i_outdriver (T) internal voltage reference,
a trimpot between pad and vdda! can be used
to increase the current in outdriver;
injected extra current : outdriver = 1 : 5

outcomm (T) internal voltage reference,
a three teminal trimpot between vddd!, pad  and vssd! can be used
to force the voltage on the node.

toutb(T)  internal voltage node, it is fixt at the
lower end of the voltage swing of the differential output drivers

tout(T)  internal voltage node, it is fixt at the
higher end of the voltage swing of the differential output drivers
 
 
 

• TEST STEPS ANALOG SECTION

Those are the first tasks of testing:

-measure internal bias nodes
-measure inpedance between different power supplies
-measure value internal resisors (Rint) plotting (TOUT-TOUTB) [V] as
   a function of IMASTER; sweep IMASTER between 4[uA] and 12[uA]
   the slope of the curve is Rint
-measure transfer function of the output buffer
-measure output buffer linearity
-treshold voltage vs. common voltage
-treshold voltage distribution
 

NOTES

-reset signal
            there is an inversion from the signal outside the chip to the signal inside of it.
            This means that in order to reset the logic from outside one has to send the sequence
            high-low-high

-chip address
            there are 7 chip_adress bits
            and they are sent to the chip MSB first

            chip_add<7>   wired internally to High
            chip_add<6>   wired internally to High
            chip_add<5>   wired internally to Low
            chip_add<4>   set externally
            chip_add<3>   set externally
            chip_add<2>   set externally
            chip_add<1>   set externally

            in the current verilog simulation the adress bits are
            HHL LHLLL
            (H=logic high;  L=logic low)

            Therefore on the pc board one should set

            chip_add<4>     -3.3
            chip_add<3>     0
            chip_add<2>     -3.3
            chip_add<1>     -3.3

Make sure that the external current sources are connected to
the proper supplies

Ifight : vdda!
Imaster : vssa!

Measurements of ifight vs imaster
 
 
 

•  ERROR LOGIC

• DIGITAL TEST PADS

• HSPICE FINAL SIMULATIONS

Last updated by Marzio Pedrali-Noy  on  Aug  / 23 / 1999.