US 7,394,869 B2 | ||
RF transmitter architecture for continuous switching between modulation modes | ||
Henrik T. Jensen, Long Beach, Calif. (US); and Brima B. Ibrahim, Aliso Viejo, Calif. (US) | ||
Assigned to Broadcom Corporation, Irvine, Calif. (US) | ||
Filed on Apr. 02, 2004, as Appl. No. 10/816,731. | ||
Prior Publication US 2005/0220218 A1, Oct. 06, 2005 | ||
Int. Cl. H03C 3/00 (2006.01) |
U.S. Cl. 375—302 [375/272; 375/279; 375/295; 375/303; 375/308] | 20 Claims |
1. A radio transmitter within a radio transceiver for producing phase-shift keyed (PSK) and frequency-shift keyed (FSK) modulated
communication signals, comprising:
a baseband processor for producing outgoing transmit (TX) data and a TX control signal;
a digital modulator that receives TX data, that digitally modulates the outgoing TX data to produce one of a frequency shift
keying (FSK) or phase-shift keying (PSK) modulated digital information signal based upon the TX control signal, wherein the
digital modulator further includes:
a modulation switching control block that receives the TX control signal, producing a modulation control signal to select
one of a plurality of types of modulation data, the modulation switching control block also producing a multiplexer (mux)
control signal to couple one of the plurality of types of modulation data to a mux output;
a pulse shaping block for producing FSK phase information based upon a first value of the modulation control signal, which
FSK phase information consists of one of a logic zero or a phase value for a FSK modulated signal based upon the TX data,
the pulse shaping block further producing I and Q modulated data based upon the TX data for a second value of the pulse modulation
control signal;
a multiplexer (mux) block coupled to receive the I and Q modulated data at a first input pair and further coupled to receive
a logic one and a logic zero at a second input pair, the mux block producing the I and Q modulated data received at the first
input pair based upon a first value of the mux control signal and for producing the logic one and logic zero received at the
second input pair based a second value of the mux control signal;
a phase accumulator coupled to receive the FSK phase information, the phase accumulator producing an accumulated phase value;
a Coordinate Rotation Digital Computer (CORDIC) block coupled to receive the accumulated phase value and further coupled to
receive the I and Q modulated data, the CORDIC block producing I and Q channel signals reflecting a phase and magnitude based
upon the accumulated phase value and the I and Q modulated data wherein the CORDIC block produces outputs in one of three
states based upon the FSK phase information and upon the I and Q modulated data and further wherein:
for a first state, the I and Q channel signals reflecting a rotated unit vector characterized by a phase reflecting the FSK
phase information;
for a second state, I and Q channel signals reflecting a vector having a phase and a magnitude based upon the I and Q modulated
data and further based upon the FSK phase information; and
for a third state, I and Q channel signals reflecting a vector having a phase and a magnitude based upon the I and Q modulated
data;
a DC offset compensation block coupled to receive the I and Q channel signals, the DC offset compensation block for pre-compensating
for expected downstream low frequency interference, the DC offset compensation block producing compensated I and Q channel
signals; and
an interpolation filter producing up-sampled I and Q channel data characterized by an output sample rate based upon an input
sample rate of the compensated I and Q channel signals;
digital to analog converter circuits for converting the up-sampled I and Q channel data to analog I and Q channel signals
having a continuous waveform;
filtering circuits for filtering the analog I and Q channel signals; and
a loop circuitry for up-converting the analog I and Q channel signals from a baseband frequency to a specified RF channel.
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