Some notes fro electronics discussion

[Melynda Brooks <mbrooks@lanl.gov>]

Hi all,

  A few notes from our electronics discussion today, mainly on action 
items, since there was too much info to repeat all the discussion. 
Agreed that next step is that Dave W. plans to make presentation of 
Nevis perspective on Thursday and then we can lead in to discussion of 
work plan.  LANL will also plan to bring details about schedule 
constraints (don't remember if we decided this online or after the end 
of the phone call).

Notes/Actioin Items:

General info in note:

Add dimensions, especially for LDRD sensors, chips.

ROC:

When considering FPGA choice should take into account cost optimization 
(and possibly availability) also.  Optimization taking into account cost 
may indicate different segmentation also.  ACTION: get some cost 
estimates along with the chip list that we already planned to get.  Make 
comparisons to alternative plans.

ACTION: Should do some work on failure analyses to see if they might 
lead to different segmentations (on our to-do list already)

ACTION: Need to indicate some fast-controls being involved with 
calibration system (to synch DAC control with data taking).

ACTION: Need to indicate clock (and all the other specific lines) going 
from ROC down to chip.  Right now just show download/readback and data 
lines with data line clock.

Explicit question about checking for memory corruption for default 
configurations.  Note mentions that we need error handling in general 
and will try to add all the specific issues that people have brought up.

ACTION: Need to determine pros and cons of various data formats out of 
ROC to FEM and pick a baseline.

FEM:

Need more explicit information from Lvl-1 guys about what segmentation 
would be desired/required.  May dictate our fiber segmenatation within a 
ROC and how we would route fibers from ROC to Lvl-1 boards.  Should 
evaluate whether Lvl-1 is putting constraints on the system that we 
would prefer to relax.  If no issues than can just plan to ship all data 
in all circumstances to Lvl-1.  If there are issues, may want to discuss 
whether we can relax any requirements or not.

Some of the to-do list which we already have which was especially 
emphasized:

--Get timing diagrams, passage of clocks worked out in some detail
--Get details of calibration system worked out
--Lay out all schedule constraints and implied milestones
--Make first (and second and...) passes on power consumption, implied 
cooling requirements and space needs and feed back in to HYTEC work
--LV/HV distribution needs to be worked out
--Ethernet control details need to be worked out

I'm sure I've forgotten something so feel free to send missing comments 
to the list,


Melynda

--

Melynda Brooks                        email:  mbrooks@lanl.gov
MS-H846, Group P-25                   office: A102, Bldg. 1, TA-53
Los Alamos National Laboratory        phone:  (505)667-6909
Los Alamos, NM  87545                 FAX:    (505)665-7920


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