(Test numbers are counted from zero. All ranges are inclusive.)
(Character # designates a number)
(Options in brackets are possible character strings.)
Unless otherwise specified, tests are done by comparing the measured value to the nominal minum and maximum. In some cases, the nominal values are adjusted before running. This will vary from run to run. Hopefully, I'll include details on those corrections soon.

If all tests (except ignored tests and digital function tests) pass, the chip is declared class A (good).
If all tests pass except for DACS, which almost passes, the chip is declared class B (probably good).
If some tests fail, the chip is declared class C (bad).
If chip is bad, but errors occur in known places, the chip is declared class D (probably good).

Contacts

Tests 0-24
25 test vectors total (I allocate space for 40 errors. Why?)

Power

Tests 25-26
2 test vectors total
Tests named SUP_SHORT:VDD[0,1]

Analog

Tests 27-60
34 test vectors total (I allocate space for 50 errors. Why?)
Tests 27-34 named IDDSB:VDD[0,1][A,B,C,D]
Tests 35-36 named V_AVDD2I[P,M]A:#/L#
Tests 37-38 named [,I]AVDD[,2]_A:AVDDP-M
Tests 39-40 named V_[V1R,N310]A:#/L#
Tests 41-46 as above, but "B" instead of "A"
Tests 47-52 as above, but "C" instead of "B"
Tests 53-58 as above, but "D" instead of "C"
Tests 59-60 named IDDOP[0,1]:[A,D]VDD

dacs

DACS tests are done differently from the other tests. The 64 negatives and 22 positives are given a linear fit, giving an intercept, a slope, and a chi-squared.
The 64(or 22) results are given x values . The chi-squared is based on assumed sigma of 0.0003.
The test looks at the slope and the chi-squared.

Tests 64-574, every sixth test
86 tests total (For some reason I store 5 errors for this.)
Tests 64-442 named CAL_IN:DAC#N, where # = 00-63
Tests 448-574 named CAL_IN:DAC#P, where # = 00-08, then 08-48 (1 every 8), then 56-63
Also looks at VTN:DAC#[N,P], which is offset by 2 from CAL_IN:DAC#[N,P]

If all of the following conditions are met, the chip is considered to have passed the test fit_parameters. Otherwise it fails.

0.008 < slope(VTN_n) < 0.120
0.004 < slope(VTN_p) < 0.008
0.006 < slope(cal_n) < 1.000
0.006 < slope(cal_p) < 1.000

If all 4 chi-squared are between 0.1 and 10, the chip is considered to have passed the test chi2. If any chi-squared is above 30, the chip fails chi2. If some chi-squared are between 10 and 30, the chip "half-passes" chi2.

If the chip passes both fit_parameters and chi2, it passes dacs.
If the chip fails either fit_parameters or chi2, it fails dacs.
If the chip passes fit_parameters and "half-passes" chi2, it "half-passes" dacs.

Digital Function Tests

Tests 577-634
58 test vectors total (I allocate space for 100 errors. Why?)
Tests all prefixed by "FUNCT@5.0V:ATOM"
(577-587): [1TO6, 7TO9][A-E], 10TO12
(588-590): 13[A, B, C]
(591-596): 14-18, 18HF
(597-603): 19, 19[B-F, FHF]
(604-610): 20-25, 25HF
(611-616): 26A, 26B, 27-30
(617-623): 31A, 31B, 32-36
(624-628): 37[A-E]
(629-634): 38-41, 41A, 42

Charge Injection (cal_inj)

Only 1 must pass to be considered good!
Tests 635-639
5 test vectors total
Tests FUNCT@5.0V:ATOM[44-48]C_40

Channel Mask (chnl_mask)

Test 640
1 test vector total
Test FUNCT@5.0V:ATOM49C_40

45D_20 (test45D_20)

Test 641
1 test vector total
Test FUNCT@5.0V:ATOM45D_20

Noise

Only 1 must pass to be considered good!
Tests 642-646
5 test vectors total
Tests FUNCT@5.0V:ATOM50_[40, 47, 48, 49, 50]

hf

Tests 647-649
3 test vectors total (I allocate space for 20 errors. Why?)
Tests FUNCT@5.0V:A[7TO9, 10TO12]HF
Test FUNCT@5.0V:ADAC37HF

tmin

Tests 651-683, every fourth test
9 test vectors total (I allocate space for 20 errors. Why?)
Tests TMIN@[4.8V, 5.0V, 5.2V]:[A7_9, A10_12, ADAC37]_50D