Summary of last weeks FVTX-DAQ/ONCS meeting

[Eric Mannel <mannel@nevis.columbia.edu>]

Dear All-

The attached file is my summary of last weeks meeting between the FVTX 
and PHENIX DAQ/ONCS groups.

Eric

--
Eric J. Mannel
Associate Research Scientist
Dept of Physics/Nevis Labs
Columbia University
914/591-2816 (office)
914/659-3235 (cell)

Summary of FVTX meeting with PHENIX DAQ/ONCS groups, Jan 30, 2008

Presentation by Sergey Butsky providing overview of FVTX integration
into the PHENIX DAQ/Online systems.

Numerology:

  IR Region:
	Number of Endcaps: 2
	Number of Disks per Endcap: 4

	Number of Wedges: 48 per disk
	Total Number of Wedges: 384

	Number of Wedges per ROC: 4
	Number of ROCs per Endcap: 12
	Total number of ROCs: 24

	Number of ROCs per Clock Distribution Board: 6
	Number of Clock Distribution boards per Endcap: 4
	Total number of Clock Distribution Boards: 8

        Number of data fibers per ROC: 1
	Total number of fibers per Endcap: 144
	Total number of fibers: 288

	Number of fibers per bundle: 12
	Number of active fibers per bundle: 8
	Number of fiber bundles per endcap: 24
	Total number of fiber bundles: 48

	Number of slow control fibers per ROC: 2
	Number of slow control fibers per endcap: 24
        Total number of slow control fibers: 48

	Number of Clock fibers per endcap: 4
	Total Clock fibers: 8

  Rack Room:
	Number of FEMs per ROC: 2
	Total number of FEMs: 48

	FEMs per Crate: 12
	Total number of crates: 4

	FEM Interface Cards:  4
	DCM-II channels(fibers): 48

Discussion/Comments:

Down load of operating parameters should incorporate a readback
mechanism to verify that there was no data corruption in the transfer
process.

Reprogamming of FPGA's on ROC's should be rare occurance, and will be
done via slow control.  

Calibration will be done at most daily.  Requires download of a few
constants to set the pulse height. Currently no readback implemented.
Discussion that a read back might be useful if the calibration results
do not match the expected results.  How do you know if it was an error
in the transfer of calibration constants or hardware?

Discussion of what happens if the reprogramming of the eeproms fails
or is interupted? Does it leave the system in a non-operational state?

Monitoring of Voltage, current and temperature will be built into the
ROC. Expect that there will be a small, 1 KByte, of data every minute
or so.  Can come up either in the slow control or data streams.

Slow control communications is exepected to be via ethernet using a
Digilent ethernet module.  Some questions about what the
communications protocol is and how easy it will be to implement in
ONCS. Documentation on the module will be circulated for evaluation.

Discussion of power and power supply needs.  Expect that LV and Bias
be segmented at the wedge level.  Power is fused and monitored on the
power distribution card.  Regulation is done on the ROC for both the
ROC and wedge. 

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