a processor providing a data access address;

a set of control registers coupled to the processor, storing memory configuration information;

a memory device comprising a plurality of entries organized by a first predetermined number of ways, wherein the processor selectively configuring a selected number less than or equal to the first predetermined number of the ways as cache memory belonging to a cacheable region, and configuring remaining ways as directly addressable memory belonging to a directly addressable region by the memory configuration information in the set of control registers; and

a memory controller coupled between the processor and the memory device, determining the data access address corresponding to the cacheable region or the directly addressable region, selecting only the way in the directly addressable region corresponding to the data access address when the data access address corresponds to the directly addressable region, selecting only the way(s) belonging to the cacheable region when the data access address corresponds to the cacheable region, and having a cache hit detection circuit comprising:

an address register storing the data access address;

a pretermined number of tag memories corresponding to the memory ways, storing tag data of the data access address provided by the processor;

a data processing device selectively outputting the tag data or an adjusted tag data as processed data according to a direct address signal; and

a pretermined number of address comparators corresponding to the memory ways and coupled to the data processing device, each of the address comparators comparing the processed data with portion bits of the data access address from the address register, and outputting an address match signal as comparison match,

wherein the processor provides the direct address signal indicating that the way is configured as the directly addressable memory, and a cache signal indicating that the way is configured as cache, and

wherein the tag data is adjusted to a pretermined address by the data processing device, which is the highest address of memory space of the processor.