Equipment Logistics Services
FIB Fanout (FFO)
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Features
The FIB Fanout provides the interface between a FIB subrack containing up to 12 FIB modules and the Silicon Readout Controller (SRC). The SRC sends commands over a 1Gb/sec optical link (GLINK) to the FIB Fanout. These commands are buffered and redriven by the Fanout to all FIB modules over a custom backplane. As the commands are transferred the Fanout continuously monitors the data for protocol errors and alerts the SRC via an RS-485 link if any errors are seen in the transmission. An Error FIFO keeps a history of data sent and stops when an error is detected to allow post-mortem diagnostics. A Test FIFO may be used to send commands to FIBs when no SRC is present to simplify diagnostics. A loop mode in the Test FIFO allows continuous execution of a stored sequence for system error rate analysis. Clock control logic in the Fanout provides a locally generated clock and command sync pulse to all FIB modules until the GLINK data indicates that an SRC is present and sending valid data. Upon receipt of a valid sequence from the SRC, the clocks and command syncs to all FIBs are momentarily halted, the FIB Fanout resynchronizes to the GLINK clock frequency, and then commands and clocks to the FIBs are resumed. On-board circuitry allows software to monitor GLINK optical power received, local temperature, local supply voltages and to test the integrity of cable connections between the SRC and the FFO. If necessary the FFO can generate, upon request from the SRC via the optical link, a reset pulse in its subrack to reset an out-of-control microprocessor. Additional Technical Information
Additional Technical Information (PDF Format) |
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For assistance contact helpdesk@fnal.gov. Information maintained by Mike Behnke; last modified on July 11, 2006. (Address comments about page to prep-webmaster@fnal.gov.) |