| US 7,361,960 B1 | ||
| Semiconductor device and method of manufacturing the same | ||
| Yoshitaka Tsunashima, Yokohama (Japan); Kiyotaka Miyano, Tokyo (Japan); and Yukihiro Ushiku, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Kawasaki-Shi (Japan) | ||
| Filed on Oct. 17, 2000, as Appl. No. 9/688,989. | ||
| Application 09/688989 is a division of application No. 09/105958, filed on Jun. 29, 1998, granted, now 6,184,083. | ||
| Claims priority of application No. 9-174205 (JP), filed on Jun. 30, 1997; application No. 10-185453 (JP), filed on Jun. 30, 1997; and application No. 10-042056 (JP), filed on Feb. 24, 1998. | ||
| Int. Cl. H01L 29/76 (2006.01); H01L 31/00 (2006.01) | ||
| U.S. Cl. 257—380 [257/393; 257/410; 257/411; 257/903] | 7 Claims |
| 1. A semiconductor device comprising:
a semiconductor substrate including a first and second region separated by an isolation element;
a first transistor formed on the first region of the substrate and including a first insulation film and a first gate electrode
arranged along a first direction; and
a second transistor formed on the second region of the substrate and including a second insulation film and a second gate
electrode arranged along the first direction,
wherein a first side wall is located at an end of the first gate electrode in the first direction, a second side wall is located
at an end of the second gate electrode in the first direction, and the first side wall is directly physically and without
the presence of additional layers therebetween connected to the second side wall above the isolation element when viewed from
a direction perpendicular to the first direction.
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