TDC bunch counter errors (10/24/98):

Frank Chlebana observed synchronization problems with the bunch counters on TDCs in the Cosmic ray test stand. Over the past 2 weeks we have been exploring these problems with the TDC Full Crate test.

General observations:

A few example tests are outlined. Configuration:

Tests performed: Note that in the last test we incremented the number of L1R by 2 and add 2 to the bunch counter for slots 4-10. This is the expected behavior. However in slot 17 it increments by 3. Adding or subtracting more L1R continues with this picture. This would lead one to believe that extra clock cycles are being generated in Slot 17.

On examination of the PC board, we discovered the PECL clock receiver is about 10" from the P2 pins. This is true of both the Rev B and Rev C boards.

Postscript files of scope pictures of Clock signal after receiver on TDC boards in crate. In all cases lower trace (blue/purple) is from Slot 17 TDC and upper trace (magenta) is from slot 3. Four configurations:

There is a clear problem in cases 1 and 2. When the TRACER is in the center of the crate the signals look about the same as if there are only 2 TDCs installed. These are consistent with reflections off the stubs on the TDC boards causing extra edges.

There are a couple of other puzzles about the bunch counter. One puzzle is the offset. There are 35 L1 rejects after the B0 has been received but the bunch counter is reading out 155. The other is that the boards that are synchronized have the bunch counter roll over from 158 to 00. The board which is out of synch does not roll over (evidenced by getting a value CA).

Added Nov 20, 1998: More Postscript files of scope pictures of Clock signal after receiver on TDC boards in crate. In all cases Blue trace is from Slot 4 TDC and Green trace is from slot 3 and the Red trace is an ADMEM in slot 16. Four configurations:

Note following on clock receiver chips on the different boards:

Created by P. Wilson (pjw@fnal.gov). (last updated Nov 20, 1998)