| Title |
Implementation of the ALICE Trigger System |
Submitted |
26-JAN-07 04:46 (UTC -06:00) |
| Classification |
Trigger and Data Acquisition |
Modified |
27-APR-07 03:52 (UTC -05:00) |
| Session |
TDAQ-Trig |
Presentation |
Oral |
| Speaker |
Pedja Jovanovic |
Paper ID |
TDAQ-Trig06 |
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Paper PDF |
Download |
| Author(s) |
Pedja Jovanovic, Anju Bhasin, David Evans, Goronwy Jones, Anton Jusko, Marian Krivda, Cristina Lazzeroni, Roman Lietava, Orlando Villalobos-Baillie (Birmingham University, Birmingham), Ivan Kralik, Ladislav Sandor (IEP SAS, Kosice), Josef Urban (P.J. Safarik University, Kosice) |
| Abstract |
The ALICE trigger processor [1] generates three levels of hierarchical hardware triggers; the 24 ALICE sub-detectors can be dynamically partitioned into up to six independent clusters that operate concurrently and independently from each other; trigger selection includes the Past-future Protection - a fully programmable hardware mechanism of controlling the event pile-up; etc. . The trigger system consists of the Central Trigger Processor (CTP) and 24 Local Trigger Units (LTU) that act as a uniform interface to sub-detector front-end electronics; in stand-alone mode, the LTUs fully emulate the trigger protocol. Great care has been given to the testability of both the components and the system as a whole: ScopeProbe and SoftLED enable centralised access to relevant internal logic signals; distributed SnapShot memories both emulate logic inputs and monitor the logic operation; a large number of signal counters, with simple on-line access, control the system performance and check the consistency. The original implementation of those options using the FPGAs is one of main topics of the presentation. |
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Word Count: 165 Character Count: 1098 |
| Footnote |
[1] ALICE CTP web site: http://www.ep.ph.bham.ac.uk/user/pedja/alice/. |
| Funding Agency |
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