E781 Trigger Logbook
February, 1997
Sat Feb 1 13:48:38 CST 1997, antonio
today I check the scaler clear unit.
I terminate the output which enters into the fan-out which feed the sca. clear
I hope the scaler t0/t0_dec get more stable.
end of run 6105
start at run 6106
Sat Feb 1 15:58:43 CST 1997, antonio
the problem of t0/gbeam still there
so I decided to declare a flaky unit 128L fan-out c62/n4 a1=broken a2=flaky
I replaced by a unit
c62/n1/a1 & a2 joerger 100A coincidence unit (it is in single input mode)
start run 6110 spill 28
Sat Feb 1 16:48:29 CST 1997, antonio
re-wired the latch for g-pulser
g-pulser is comming from output t0_dec_plu # 6
in this way I only see gpulser if t0 aproved it
Now it is much better
however IT will get forwarded t1 and t2 ONLY under bypass
to fix this I may attemp to install gpulser final decition in t2
QUESTION how do I forward the t0 to t1 to t2 TRICKY
antonio
same TRICKY to forward all other
t0 or t1 stuff
how do I collect memory of the flow !
Sun Feb 2 19:09:47 CST 1997, antonio
put clear in scaler 4434 22 08 32 clear T0 T1 ...
start run 6165 Spill 17
I hope there will constant t0/t0srs_8
Sun Feb 2 20:22:54 CST 1997, antonio
I fine tune the
NOT_T1, remove 8 ns between c63n7a2 and c63n7a1
NOT_T2, change from 1 to 8 ns between c64n4a3 and c64n4a1
change from 5 to 2 ns between c64n4a1 and c64n5a4
There are a few spills where (NOT_T1+T1)/T0 is 2 runs 4600 to 6200
There are a few spills where (NOT_T2+T2)/T1 is 2 runs 4600 to 6200
I have not check earlier runs.
start run 6165 Spill 97
Mon Feb 3 17:51:08 CST 1997, antonio
The trigger
Interaction
Beam
Lpulser
Gpulser (include a re-wiring of Latch, now comming from t0_dec_plu#6)
Random
now are all set to v5.1 the common change which will produce only a
2 nanosecond improvemente for the V chambers in the Interaction trigger is
v5 from a delay of 5 was reduced to 3 (gain 2 nanoseconds such s3
will drive timing in Interaction)
s4q from a delay of 12 was reduced to 3 (this will center the veto_s4q)
the changes are valid (including) from run 6193
(only Interaction will show the improvement others do not use v5)
antonio
Wed Feb 5 12:38:09 CST 1997, antonio
review scaler clear NOW I check that clear soft (do not wired clear hardware)
4434 22 08 32 clear T0 T1 ! important for monitoring / soft
4434 20 6 32 clear S1a VH1a ! monitoring / soft
85 22 19 4 no clock trigs
4434 20 20 32 clear T0srs_1 T0srs_2 ! important for monitoring / soft
4434 20 21 32 clear btrd01 btrd02 ! / soft
4434 22 01 32 no H2p_01 H2p_02
4434 22 02 32 no H2m_01 H2m_02
4434 22 03 32 no H1m_01 H1m_02
4434 22 04 32 no H1p_01 H1p_02
4434 22 05 32 no s22_01 s22_02
4434 22 06 32 no s22_21 s22_22
4434 34 7 32 clear pwc_X1 pwc_Y1 ! / soft
85 22 10 4 no T1_sil T2_sil
85 20 3 4 clear s_20_3_1 accide ! / soft
85 20 22 4 no SLRes MRes
85 35 5 4 clear veeau veeay ! / soft
85 35 6 4 clear veebv veeby ! / soft
85 35 7 4 clear veecu veecy ! / soft
85 20 4 4 no SResIn PLU_clr
Thu Feb 6 00:02:17 CST 1997, antonio
Starting 6292 Interaction default is v5.5,
it includes the merge of hadron-electron with charm trigger
Charm trigger is unchanged as yield t1/gb keeps its original value when
the hadron-electron trigger bit is masked out, see numbers below.
When the input patern of ic_mlu and t1_dec_plu has overlaping of
hadron-electron and charm I favor the charm trigger to keep t1/gb for
charm as previous normal run.
Please Klaus and Ivo, enjoy your data.
Run Spill T1/gbeam Interaction comentary
6289 694 0.01427 v5.1 normal run
6289 698 0.01419 v5.5 new version
6291 3 0.01459 v5.5 new version
6291 14 0.01401 v5.5 new version ONLY CHARM
6291 18 0.00004 v5.5 new version ONLY hadron-electron
Thu Feb 6 01:12:56 CST 1997, antonio
Instalation of pt3a at t1_dec_plu has been done.
I am using input 4 in t1_dec_plu which corresponds to 2nd bi in h1_high=h2_mult
Right now it is the easiest way to have the pt3a and the ic's h1,2' and btrd
in a set of logical function (to be programed by Victor Steiner).
This pt3a emulates the hst, RIGHT now there is not certainty at what time
the hst decition will be done. Also Victor Golovostov is looking to include
IC and H1,2 into the HST procesor itself in such a way that HST will
produce the final decition.
Now, let's see how much Prima-team can learn with pt3a at t1_dec in stand-alone
trigger & runs.
Thu Feb 6 16:21:35 CST 1997, antonio
I touch in/out the atenuators which make trigger hi_mult and h1_high decition
then the trigger get out of sink.
PLEASE NEVER AGAIN TOUCH THIS ATENUATORS
h1_high (input 11) > 12 went counting high than the two previous (>8 >11)
supresing the trigger to t1/gb=0.010.
A way to patch was made removing the "> 12" from the or of the trigger.
The trigger now is producing t1/gb=0.012 (yesterday v5.1 produced 0.014)
Sat Feb 8 19:07:05 CST 1997, antonio
the t0 is showing lock in the read_busy and the life goes down
It happens one spill yes a fe others ok.
control access from 6 to 7 PM
) next time this problem sugest change t0_plu
I DID NOT replaced it,
no spares in schoolhouse neither pit
) I only reset the crate 20 on/off
) also reset crate 60 on/off
) under the pulser the problem is not seen.
At the same time I corrected the t2_dec input_one (strobe)
now is 20 ns wide and arrives on time to match the t2_done t2_full circuit.
install clear in scaler c22n6, now it is ok
also softly push the h1_high atenuators, looks it now recovered
H12_09 365342. H12_10 226936. H12_11 163321. H12_12 13247.
Thu Feb 13 10:20:36 CST 1997, antonio
now most of the 4434's clear on wire, it is important to have straight the
counting of the experiment.
I hope several camac problems get alivated, or at least NOT disturbing.
4434 22 08 32 no T0 T1
4434 20 6 32 no S1a VH1a
85 22 19 4 no clock trigs t
4434 20 20 32 no T0srs_1 T0srs_2
4434 20 21 32 no btrd01 btrd02
4434 22 01 32 no H2p_01 H2p_02
4434 22 02 32 no H2m_01 H2m_02
4434 22 03 32 no H1m_01 H1m_02
4434 22 04 32 no H1p_01 H1p_02
4434 22 05 32 no s22_01 s22_02
4434 22 06 32 no s22_21 s22_22
4434 34 7 32 clear pwc_X1 pwc_Y1
85 22 10 4 no T1_sil T2_sil
85 20 3 4 clear s_20_3_1 accide
85 20 22 4 clear SLRes MRes
85 35 5 4 clear veeau veeay
85 35 6 4 clear veebv veeby
85 35 7 4 clear veecu veecy
85 20 4 4 clear SResIn PLU_clr
Thu Feb 13 12:33:10 CST 1997, antonio
UPGRADE: In trigger configuration.
The upgrade was required to have a set of latches gated at T1
(previously a unique gate was given to all of them, and a lot of
head ache I was having holding signals, the present option just
holds the gate and DONE, a dream on that !)
lathes
A 1
A 2
A 3
A 4
A 5 T2 t2 fan out
A 6 1/100 scc2; pulser run 2757, shows the prescale 1/100,
from 10000, 100 scc2's
A 7 G pulser
A 8
A 9 charm_t2 from 0 t2_psps 1 t2_mlu_dec (1-16)
A 10 1 t2_psps 2 t2_mlu_dec (1-16)
A 11 2 t2_psps 3 t2_mlu_dec (1-16)
A 12 t1_bypass 3 t2_psps
A 13
A 14
A 15
A 16
B 1-16 directly from t2_mlu_dec
B 1 into 0 t2_psps may trigger depending on psps mask
B 2 into 1 t2_psps may trigger depending on psps mask
B 3 into 2 t2_psps may trigger depending on psps mask
B 4
B 5 matrix
B 6 matrix
B 7 matrix
B 8 matrix
B 13
B 14 pbg sum
B 15
B 16
C 1 charm_t1 from 0 t1_psps
C 2 1 t1_psps used for pt3a scintillator
C 3 2 t1_psps pluged into nim/ecl t1_dec 3 (1-16)
C 4 t0-bypass 3 t1_psps
C 5
C 6
C 7
C 8
C 9-16
Thu Feb 13 19:07:33 CST 1997, vjs
During the Open Access today, I moved the H2 hodoscope 1.8cm to the East,
so that the -ve beam goes through the symmetry axis of the hodoscope. This
is how it was supposed to be installed, but further study of the best
position of the hodoscope is continuing.
Thu Feb 13 21:44:21 CST 1997, antonio
the latch correction uses the same gate as the adc camac.
It is 100ns and at 258ns.
The entrance of the latch is at 233 then a 32 ns cable delay to enter
latch at 265, enough coverage to guarrantie one pulse per event.
Thu Feb 13 21:49:32 CST 1997, antonio
I check the signals in the matrix, turning on/off H2 and H1 elements.
Looking them at the scalers.
On my two attemps ma_01 and ma_02 I saw reduction of 25 to 50 % something
which was not worth mentioned since it is high off the common sense.
Well I just realize that my problem was that H2 multiplicity of 8 does not
fit in three bits and then "0" was showing, faking the reduction, this
efect I saw in the scaler counting turning on/off H2 and H1 elements.
I am in the process to prepare another
pair of triggers to account for the 8==0.
Sun Feb 16 16:41:56 CST 1997, vjs
Hodoscope counter H2-44 has been dead since Thursday's access.
During a short access today I checked to see if the problem is
with the counter, the cables, or the discriminators, by exchanging
cables with neighbouring counters. I conclude the problem is
inside the box. All cables are back to normal. I have turned off
the HV of H2-44 for a while, to see if it recovers.
Sun Feb 16 18:41:46 CST 1997, antonio
trigger_load was updated to load_scc when manually issued trigger_load
trigger_load was upgraded to show TRIGGER_LOADING while loading.
Mon Feb 17 13:44:23 CST 1997, Alex
cplu v1_01
environment variable TRIG_CONFIG used for compilation to use
the same source code for different output *.hex functions
cpluc source.c "-Dflag1 -Dflag2" out.hex
sh interface to cplu - Conditional compilation of PLU source.
Wed Feb 19 19:00:30 CST 1997, antonio, aik
the zero=64 in c22 was due to a BAD 84 Jorway scaler.
We swapped and now things are ok.
There was a NOT_T2 cable UNTERMINATED on the CROS area casuing double
counting in not_-t2 scalers.
In the middle we unconnect/reconect cable #33 TDC, IT IS T1 for them.
still working in v5 oscilloscope
still to work in t1_done t1_full and t2_done t2_full coincidence as
the not_xxxx timming.
the changes apply to run 6818 and higher
Wed Feb 19 19:36:18 CST 1997, antonio
Gpulser upgraded to catch all the beam, nothing stops the pulser
presently random from PULSER_GENERATOR at 53 MHz, prescaled
lrwxr-xr-x 1 morelos trigger 12 Feb 19 19:28 Gpulser -> Gpulser_v5.2/
drwxrwxr-x 2 morelos trigger 1024 Feb 19 19:17 Gpulser_v5.2/
Wed 19 Feb 1997 19:56:48 vjs
It seems that my recipe for H2-44 (turn its volts down for a while)
was successful....it has been working since run 6809, this morning.
I didn't actually turn the volts back up myself, someone must have
loaded the hvs at the standard settings: anyway, it works now !
It is interesting (and equally mysterious), that counter H2-31
stopped working during run 6810, but has been fine again since.
Thu Feb 19-20 16:01:03 CST 1997, antonio aik
after the 8 ns extra into the Level_PLU strobe (last part of matrix)
we did the following checkups.
run spill trigger T2/T1 tgt t0/gb t1/gb
6822 83 I v5.5 IN 0.03528 0.0117
88-91 ma_05 0.85 IN ! why am I rejecting
92-93 ma_05 0.85 OUT ! reduce rate matrix reject same
96 ma_05 IN ! ok
A good point, since present matrix is only h1+ then mask "0" h1_0
run spill trigger T2/T1 tgt t0/gb t1/gb
6822 102-103 ma_05 0.88 IN ! YES it increase
! the effect of the "zero"
! is the differnce = 0.03 o 3 %
! what I saw in offline OFF
! WHAT IS THE REST 12% looses !
6822 107-109 ma_05 0.89 IN ! all othere H's mask out
6822 112 ma_05 0.89 IN ! IC's from -1300 to -1600
the following are tests where ONES are installed to check timming
run spill trigger T2/T1 tgt t0/gb t1/gb
6822 122 ma_05 1 ! t2_dec_mlu ONES
! testing the T2 done/FULL
6822 132 ma_05 1 ! Level PLU ones
! testing the strobe into T2_mlu
Thu Feb 20 17:00:03 CST 1997, antonio
trigger_load has been upgraded to load_scc before the last message is sent
to share-memory
Sat Feb 22 22:45:26 CST 1997, antonio
Trigger upgrade:
The problem of missing camac ADC is still there.
I made a control acces to center the signals
full_T1 and done_t1 (for case charm and t0_bypass), and the equivalente ones
for the NOT case. A review exercise I did on the T2 equivalent cases.
I pushed by 8 ns more the signal t1_done
This causes to eat 8 ns from the spare hidden 24 ns
So we have now only 16 ns hidden spare.
T1 fan_out is preserved at 283 ns AS USUAL
WARNING the camac ADC's gate was moved from 258-> 267 ns and on the
oscilloscope the IC's signals are just on time,
NOW I UNDERSTAND THE importance of T1_FOUT @ 283 !
I expect that there will be less missing=zerosx with the camac ADC's.
STARTING run 6943 (inclusive)
antonio
ps:I need to produce another trigger drawing showing updated timming.
Sun Feb 23 19:25:21 CST 1997, antonio, aik
misses misses
run IC1_scc1 1/100 IC1 trigger
6982 0.0 0.0 Lpulser
6984 0.0 0.0 Lpulser same prescale as Beam 100/2
6772 0.0 0.0 Gpulser
6978 40% 40% Beam !!!!!!!!!!!!!!!!!!!
the problem with beam IT IS STILL THERE
so the experts continue the search
Sun Feb 23 23:39:31 CST 1997, antonio
6818 0.0 0.0 Gpulser with particle beam
6986 43% --- Beam prescale t0_by 1/ t1_by 500
run IC1c1 1%IC1 T0 trigger
6987 41% 38% 2.3e6 Beam prescale t0_by 500 t1_by 1 1/100 1 fallo
6888 0.5% !!!! 29931 Beam prescale t0_by 1 t1_by 1 1/100 1 DE_TUNE
for very low intensity beam
Well looks I uncover a trick on the camac_ADC_rate relation, let's read:
From Mao's ADC's and TDC's in E781 write up
fastbus ADC " Fast clear. ... The next signal can be accepted in about 800 ns
after the clear"
at 2e7 pps (particles per spill) o 1 Mhz hyperon beam there will
events every 1 microsecond, while the trigger minimun time-difference
between previous event t1_clear and new event t1 is approx 400 ns.
I will say that in life-average the fastbus ADC are just enough in E781
fastbus TDC " ... The new event can be accepted in 250ns after the previous
event is cleared"
The fastbus TDC easily survive in E781 enviroment.
From the 2 pages 2249A
camac ADC 2249A: " Fast Clear: ... REQUIRES ADDITIONAL 2.0 MICROSECONDS AFTER
CLEAR "
Hyothesis: The zeros in the camac_ADC's are due to the fact that the
clear operation is not completed within the 2 microsec.
PROFF: the low intensity run I did, see above.
WE CAN NOT AFFORD THE 2 microsecond since we want to run at 20e7 pps o
1 MHz hyperon beam. What to do:
a) continue as we are, when people need ADC info run low intensity
b) another technology, IS IT WORTHED THE EFFORT ?
Mon Feb 24 14:22:29 CST 1997, Alex.
*** Access to PC4:
1) GG 2323 for SRes TO was changed in crate 20 - no effect;
50 ohm terminator was inserted to bridged input - now it works. !!!
So, it was stolen/loosed sometime and now recovered.
2) Moved clear signal to camac ADC from not_t1 to not_T2 (as ADC is
started by T1).
*** V5 HV/delay scan. - file v5-scan-III.txt
HV set to =1800 ( was -1550 )
delay to 10 ns (was 2ns)
*** Scale factor for T1/T2 was changed from 2 to 1 for Beam trigger (Jim requested).
Before RUN #7014
Mon Feb 24 15:29:53 CST 1997, antonio
Aik: I rather change t1_trigger psps to set the rigth numbers of T2
It is usefull to exercise the NOT_T2 case to keep us on shape.
t0_bypass(before100)
t1_trigger:load_psps 24 20 08 0 0 0 50
t1_bypass(2 ok)
t2_trigger:load_psps 25 10 08 0 0 0 2
Tue Feb 25 17:30:57 CST 1997, antonio
matrix input now is as:
most postive region H1+ bits 3-16 in 7106 latch into c24n7 = enable B
H1+ bits 3-10 H10 bits 8-16 latch into c24n6= enable A
From morelos Wed Feb 26 13:30:12 1997
More trigger era's (hopefully soon we reach a real improvement !)
For a while just releasing
Beam_v5.6 RUN 7078 INCLUDED
Interaction_v5.6
Both of them have the BTRD latches, located in the very last three bits,
as shown below.
This is an early bird stage.
I DO EXPECT people look in them (JE and NT, in particular) and let me know
your analysis, either positive or negative.
enjoy, antonio
lathes
A 1
A 2
A 3
A 4
A 5 T2 t2 fan out
A 6 1/100 scc2; pulser run 2757, shows the prescale 1/100,
from 10000, 100 scc2's
A 7 G pulser
A 8
A 9 charm_t2 from 0 t2_psps 1 t2_mlu_dec (1-16)
A 10 1 t2_psps 2 t2_mlu_dec (1-16)
A 11 2 t2_psps 3 t2_mlu_dec (1-16)
A 12 t1_bypass 3 t2_psps
A 13
A 14
A 15
A 16
B 1-16 directly from t2_mlu_dec
B 1 into 0 t2_psps may trigger depending on psps mask
B 2 into 1 t2_psps may trigger depending on psps mask
B 3 into 2 t2_psps may trigger depending on psps mask
B 4
B 5 matrix
B 6 matrix
B 7 matrix
B 8 matrix
B 13
B 14
B 15
B 16 pbg sum
C 1 charm_t1 from 0 t1_psps
C 2 1 t1_psps used for pt3a scintillator
C 3 2 t1_psps pluged into nim/ecl t1_dec 3 (1-16)
C 4 t0-bypass 3 t1_psps
C 5
C 6
C 7
C 8
C 9
C 10
C 11
C 12
C 13
C 14 MAJ 1 btrd
C 15 MAJ 2 btrd
C 16 MAJ 1 and MAJ 2m btrd
Wed Feb 26 18:35:15 CST 1997, antonio
In Interaction v5.6 there is a WIDE MATRIX loaded, still bypassed, it
goes to a latch. Study it and find about what kind of events are being lost
(suggest look run 7085 Iv5.6 unfilter)
run spill t0/gb t1/gb t2/gb t2/t1
7088 27 0.19044 0.01336 0.01131 0.87 ma_07 ok I see the rejection
7089 1 data ok lost spill
2/3/4 lost spill
5-6 0.188 0.0135 0.01147 0.0848 ma_07
Wed Feb 26 18:53:00 CST 1997, Alex
I changed V5 HV in std-beam.hv for few more triggers
to be the same -1800 V:
Gpulser/Lpulser/Random
in addition to
Beam and Interaction.
Really changing something common for few controlled configurations becames
confusing.
Thu Feb 27 20:22:02 CST 1997, antonio
There was game hv delay, the newest is ok, by aik and tdc's
Just checking charm in/out, h-e, only , life t's/gb
run spill trigger tgt condition T0/gb T1/gb live ch_t1/gb he_t1/gb
7118 71-72 Iv5.6 in normal 0.18159 0.01444 0.47791 0.12614 0.00889
7118 74 Iv5.6 in only_charm 0.17279 0.01444 0.48828
'' 76-77 '' OUT only_charm 0.14545 0.00177 0.69354
78-79 '' in only_charm
7118 80-81 '' in only_h-e 0.17997 0.00045 0.70817
Fri Feb 28 02:08:32 CST 1997, antonio
I installed the new camac adc
starting run 7131 (inclusive)
Please have a look, monitoring is enough
also installed delay 4418 for photon sum signal before entering the t2_dec_mlu
(1 unit = 1 ns goes from 0 to 31)
VS and I chained 2 channels to go up to 0 - 62 ns.
VS will look into the delay curve for photon sum.
HTML version:
aik@fnal.gov
Fri Jan 9 15:43:57 CST 1998