---

sysLib.c

Go to the documentation of this file.

/* sysLib.c - Motorola MVME2100 board series system-dependent library */
/* Copyright 1984-2000 Wind River Systems, Inc. */
/* Copyright 1996-2000 Motorola, Inc. All Rights Reserved */

/*
modification history
--------------------
* #ifdef APS_BSP
aps,06jul01,anj  APS mods.
* #endif  APS_BSP 
01u,14jul00,rcs  fixed path to pciConfigShow.c
01t,15jun00,dmw  updated following WRS code review.
01s,08feb00,rhk  Modified sysMemProbeBus to allow the vxMemProbe call
                 to work properly.
01r,25jun99,srr  remove #ifdef INCLUDE_PCI_AUTOCONF around sysDynEnetFind.
01q,24jun99,srr  reset the EPIC in sysToMonitor.
01p,23jun99,srr  restored call to sysUniverseInit2 in sysProcNumSet.
01o,21jun99,srr  added support for running PCI Auto Config in bootrom only.
01n,04jun99,rhk  removed the "ifdef INCLUDE_END"s, changed dec214x to
                 dec21x40, removed the routine sysDec21x40EnetAddrGet, 
                 removed addition of SERIAL_INTERRUPT_BASE value from 
                 calculations of ivec and ilevel, moved the sysUniverseInit2
                 call from sysProcNumSet to sysHwInit2.
01m,29apr99,rhk  changes to support the Tornado 2 environment and SENS.
01l,28apr99,dmw  Removed trigraph in sysPhysMemTop and replaced dynamic
                 memory sizing with a real routine.
01k,16apr99,rhk  changed PCI_xxx define names, changed page table window
                 sizes, changed VME LM define names.
01j,08apr99,dmw  added VPD code.
01i,05apr99,rhk  removed legacy code, moved the xxxSpd routines to 
                 sysSpeed.c.
01h,12mar99,rhk  changes for Shared memory support, removed EIEIO_SYNC macro
                 and replaced with SYNC macro.
01g,24feb99,rhk  added PCI autoconfiguration support, setup UNIVERSE for PCI
                 autoconfig and removed UNIV I legacy code.
01f,17feb99,srr  Added SENS support.
01e,17feb99,rhk  removed speed functions.
01d,15feb99,rhk  removed last instances of IBC references.
01c,12feb99,rhk  more legacy cleanup, setup for auxclk, used the MV2400
                 version of sysLib.c as a basis for mods.
01b,08feb98,rhk  updated the page table entries (sysPhysMemDesc) for mv2100
                 and started removing legacy code.
01a,11dec98,srr  created. (from ver 02h of mv2600/sysLib.c bsp)
*/

/*
DESCRIPTION
This library provides board-specific routines.  The chip drivers included are:

    i8250Sio.c - Intel 8250 UART driver 
    ppcDecTimer.c - PowerPC decrementer timer library (system clock)
    byteNvRam.c - byte-oriented generic non-volatile RAM library
    pciConfigLib.c - PCI configuration library
    universe.c - Tundra Universe chip VME-to-PCI interface library
    kahluaEpic.c - Kahlua Interrupt Controller
    sysI2cDrv.c - Kahlua I2C interface driver

INCLUDE FILES: sysLib.h

SEE ALSO:
.pG "Configuration"
*/

/* includes */

#include "vxWorks.h"
#include "vme.h"
#include "memLib.h"
#include "cacheLib.h"
#include "sysLib.h"
#include "config.h"
#include "string.h"
#include "intLib.h"
#include "esf.h"
#include "excLib.h"
#include "logLib.h"
#include "taskLib.h"
#include "vxLib.h"
#include "tyLib.h"
#include "drv/end/dec21x40End.h"
#include "arch/ppc/archPpc.h"
#include "arch/ppc/mmu603Lib.h"
#include "arch/ppc/vxPpcLib.h"
#include "arch/ppc/excPpcLib.h"
#include "private/vmLibP.h"
#include "drv/pci/pciConfigLib.h"
#include "kahluaMemParam.h"
#include "sysMotVpd.h"

/* defines */

#define ZERO    0


/* globals */

/*
 * sysBatDesc[] is used to initialize the block address translation (BAT)
 * registers within the PowerPC 603/604 MMU.  BAT hits take precedence
 * over Page Table Entry (PTE) hits and are faster.  Overlap of memory
 * coverage by BATs and PTEs is permitted in cases where either the IBATs
 * or the DBATs do not provide the necessary mapping (PTEs apply to both
 * instruction AND data space, without distinction).
 *
 * The primary means of memory control for VxWorks is the MMU PTE support
 * provided by vmLib and cacheLib.  Use of BAT registers will conflict
 * with vmLib support.  User's may use BAT registers for i/o mapping and
 * other purposes but are cautioned that conflicts with cacheing and mapping
 * through vmLib may arise.  Be aware that memory spaces mapped through a BAT
 * are not mapped by a PTE and any vmLib() or cacheLib() operations on such
 * areas will not be effective, nor will they report any error conditions.
 *
 * Note: BAT registers CANNOT be disabled - they are always active.
 * For example, setting them all to zero will yield four identical data
 * and instruction memory spaces starting at local address zero, each 128KB
 * in size, and each set as write-back and cache-enabled.  Hence, the BAT regs
 * MUST be configured carefully.
 *
 * With this in mind, it is recommended that the BAT registers be used
 * to map LARGE memory areas external to the processor if possible.
 * If not possible, map sections of high RAM and/or PROM space where
 * fine grained control of memory access is not needed.  This has the
 * beneficial effects of reducing PTE table size (8 bytes per 4k page)
 * and increasing the speed of access to the largest possible memory space.
 * Use the PTE table only for memory which needs fine grained (4KB pages)
 * control or which is too small to be mapped by the BAT regs.
 *
 * #ifndef APS_BSP
 * The BAT configuration for 4xx/6xx-based PPC boards is as follows:
 * All BATs point to PROM/FLASH memory so that end customer may configure
 * them as required.
 *
 * #endif  APS_BSP 
 * [Ref: PowerPC Programming Reference, 7-25, 7.4.1]
 * #ifdef APS_BSP
 *
 * The BAT configuration for APS mv2700 boards is as follows:
 *   BATs are set up to access 1Gb of uncached, guarded VME A32 space.
 * #endif APS_BSP
 */

UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT)] =
    {
#ifndef APS_BSP
    /* I BAT 0 */

    ((ROM_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | (_MMU_UBAT_BL_1M &
    ~(_MMU_UBAT_VS & _MMU_UBAT_VP))),
    ((ROM_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
#else /* APS_BSP */
    ((VME_A32_MSTR_BAT0 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256M |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((VME_A32_MSTR_BAT0 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
#endif /* APS_BSP */
    _MMU_LBAT_CACHE_INHIBIT),

    /* I BAT 1 */
#ifdef APS_BSP
    ((VME_A32_MSTR_BAT1 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256M |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((VME_A32_MSTR_BAT1 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_CACHE_INHIBIT),
#endif /* APS_BSP */

#ifndef APS_BSP
    0, 0,

#endif /* APS_BSP */
    /* I BAT 2 */
#ifdef APS_BSP
    ((VME_A32_MSTR_BAT2 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256M |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((VME_A32_MSTR_BAT2 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_CACHE_INHIBIT),
#endif /* APS_BSP */

#ifndef APS_BSP
    0, 0,

#endif /* APS_BSP */
    /* I BAT 3 */
#ifdef APS_BSP
    ((VME_A32_MSTR_BAT3 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256M |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((VME_A32_MSTR_BAT3 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_CACHE_INHIBIT),
#endif /* APS_BSP */

#ifndef APS_BSP
    0, 0,

#endif /* APS_BSP */
    /* D BAT 0 */
#ifdef APS_BSP
    ((VME_A32_MSTR_BAT0 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256M |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((VME_A32_MSTR_BAT0 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED),
#endif /* APS_BSP */

#ifndef APS_BSP
    0, 0,

#endif /* APS_BSP */
    /* D BAT 1 */
#ifdef APS_BSP
    ((VME_A32_MSTR_BAT1 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256M |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((VME_A32_MSTR_BAT1 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED),
#endif /* APS_BSP */

#ifndef APS_BSP
    0, 0,

#endif /* APS_BSP */
    /* D BAT 2 */
#ifdef APS_BSP
    ((VME_A32_MSTR_BAT2 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256M |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((VME_A32_MSTR_BAT2 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED),
#endif /* APS_BSP */

#ifndef APS_BSP
    0, 0,

#endif /* APS_BSP */
    /* D BAT 3 */
#ifndef APS_BSP

    0, 0
#else /* APS_BSP */
    ((VME_A32_MSTR_BAT3 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256M |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((VME_A32_MSTR_BAT3 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED)
#endif /* APS_BSP */
    };

/*
 * sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array
 * used by the MMU to translate addresses with single page (4k) granularity.
 * PTE memory space should not, in general, overlap BAT memory space but
 * may be allowed if only Data or Instruction access is mapped via BAT.
 *
 * Address translations for local RAM, memory mapped PCI bus, memory mapped
 * VME A16 space and local PROM/FLASH are set here.
 *
 * PTEs are held, strangely enough, in a Page Table.  Page Table sizes are
 * integer powers of two based on amount of memory to be mapped and a
 * minimum size of 64 kbytes.  The MINIMUM recommended Page Table sizes
 * for 32-bit PowerPCs are:
 *
 * Total mapped memory          Page Table size
 * -------------------          ---------------
 *        8 Meg                      64 K
 *       16 Meg                     128 K
 *       32 Meg                     256 K
 *       64 Meg                     512 K
 *      128 Meg                       1 Meg
 *      .                               .
 *      .                               .
 *      .                               .
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 *
 */

PHYS_MEM_DESC sysPhysMemDesc [] =
    {
    {
    /* Vector Table and Interrupt Stack */

    (void *) LOCAL_MEM_LOCAL_ADRS,
    (void *) LOCAL_MEM_LOCAL_ADRS,
    RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE |
    VM_STATE_MEM_COHERENCY
    },


    {
    /* Local DRAM */

    (void *) RAM_LOW_ADRS,
    (void *) RAM_LOW_ADRS,
    LOCAL_MEM_SIZE -  RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE |
    VM_STATE_MEM_COHERENCY
    },

    /* Access to PCI ISA I/O space */

    {
    (void *) ISA_MSTR_IO_LOCAL,
    (void *) ISA_MSTR_IO_LOCAL,
    ISA_MSTR_IO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },

    /* Access to PCI I/O space */

    {
    (void *) PCI_MSTR_IO_LOCAL,
    (void *) PCI_MSTR_IO_LOCAL,
    PCI_MSTR_IO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },

    /* Access to PCI ISA memory space */

    {
    (void *) PCI_MSTR_MEMIO_LOCAL,
    (void *) PCI_MSTR_MEMIO_LOCAL,
    PCI_MSTR_MEMIO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },

    /* Access to PCI memory space */

    {
    (void *) PCI_DYNAMIC_MEM_LOCAL,
    (void *) PCI_DYNAMIC_MEM_LOCAL,
    PCI_DYNAMIC_MEM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },


#ifndef APS_BSP
    {
    /* MODIFY A32 VME WINDOW HERE */
    (void *) VME_A32_MSTR_LOCAL,
    (void *) VME_A32_MSTR_LOCAL,
    VME_A32_MSTR_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },
#else /* APS_BSP */
    /* VME_A32_MSTR_LOCAL entry removed, system uses sysBatDesc instead */
#endif /* APS_BSP */

    {
    (void *) VME_A24_MSTR_LOCAL,
    (void *) VME_A24_MSTR_LOCAL,
    VME_A24_MSTR_SIZE,
#ifndef APS_BSP
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
#else /* APS_BSP */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
#endif /* APS_BSP */
    },

#ifndef APS_BSP
    {
    /* Off-board VME LM/SIG/Semaphore Regs */

    (void *) VME_LM_MSTR_LOCAL,
    (void *) VME_LM_MSTR_LOCAL,
    VME_LM_MSTR_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },
#else /* APS_BSP */
    /* A32 VME LM/SIG/Semaphore Regs removed */
#endif /* APS_BSP */

    {
    /* Kahlua registers */

    (void *) KAHLUA_EUMB_BASE,
    (void *) KAHLUA_EUMB_BASE,
    KAHLUA_EUMB_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },

    {
#ifndef APS_BSP
    (void *) VME_A16_MSTR_LOCAL,
    (void *) VME_A16_MSTR_LOCAL,
    VME_A16_MSTR_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
#else /* APS_BSP */
    (void *) VME_A16_MSTR_LOCAL,
    (void *) VME_A16_MSTR_LOCAL,
    VME_A16_MSTR_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
#endif /* APS_BSP */
    },

    {
    /* PCI interrupt acknowledge */

    (void *) PCI_MSTR_IACK_WNDW_ADRS,
    (void *) PCI_MSTR_IACK_WNDW_ADRS,
    PCI_MSTR_IACK_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },

#ifdef CHRP_ADRS_MAP
    {
    /* PCI Configuration Address Register */

    (void *) PCI_MSTR_PRIMARY_CAR,
    (void *) PCI_MSTR_PRIMARY_CAR,
    PCI_MSTR_PRIMARY_CAR_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },

    {
    /* PCI Configuration Data Register */

    (void *) PCI_MSTR_PRIMARY_CDR,
    (void *) PCI_MSTR_PRIMARY_CDR,
    PCI_MSTR_PRIMARY_CDR_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },
#endif

#ifndef CHRP_ADRS_MAP /* if PReP address map */
    {

    /* map in direct access of PCI configuration space */

    (void *) PCI_MSTR_DIRECT_MAP_ADRS,
    (void *) PCI_MSTR_DIRECT_MAP_ADRS,
    PCI_MSTR_DIRECT_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },
#endif

#ifndef APS_BSP

    {
    (void *) FLASH_BASE_ADRS,
    (void *) FLASH_BASE_ADRS,
    FLASH_MEM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE  | VM_STATE_CACHEABLE_NOT
    },
#else /* APS_BSP */
    /* Soldered Flash, Read-only (programmed from PPC-bug) */

    {
    (void *) FLASH1_BASE_ADRS,
    (void *) FLASH1_BASE_ADRS,
    FLASH1_MEM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE_NOT  | VM_STATE_CACHEABLE
    },
#endif /* APS_BSP */

#ifdef APS_BSP
    /* Socketed Flash, Read-only */

    {
    (void *) FLASH0_BASE_ADRS,
    (void *) FLASH0_BASE_ADRS,
    FLASH0_MEM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE_NOT  | VM_STATE_CACHEABLE_NOT
    },

    /* System I/O registers */

    {
    (void *) MV2100_SIO_BASE,
    (void *) MV2100_SIO_BASE,
    MV2100_SIO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    }
#endif /* APS_BSP */
    };

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);

int    sysBus      = VME_BUS;           /* system bus type */
int    sysCpu      = CPU;               /* system CPU type (MC680x0) */
char * sysBootLine = BOOT_LINE_ADRS;    /* address of boot line */
char * sysExcMsg   = EXC_MSG_ADRS;      /* catastrophic message area */
int    sysProcNum;                      /* processor number of this CPU */
int    sysFlags;                        /* boot flags */
char   sysBootHost [BOOT_FIELD_LEN];    /* name of host from which we booted */
char   sysBootFile [BOOT_FIELD_LEN];    /* name of file from which we booted */
UINT   sysVectorIRQ0  = INT_VEC_IRQ0;   /* vector for IRQ0 */
BOOL   sysVmeEnable   = FALSE;          /* by default no VME */
int    pciToVmeDev;                     /* PCI to VME Bridge Device */
#ifdef APS_BSP
LOCAL PART_ID a24memPartId = NULL;
LOCAL ULONG a24memBase;
LOCAL ULONG a24memBound;
LOCAL ULONG a24adrOffset;       /* local address = VME address + offset */
LOCAL ULONG a24vmeBound;
#endif /* APS_BSP */

/* last 5 nibbles are board specific, initialized in sysHwInit */

unsigned char lnEnetAddr [6] = { 0x08, 0x00, 0x3e, 0x00, 0x00, 0x00 };
unsigned char clearWd [1]  = { 0x00 };

#if defined(INCLUDE_PMC_SPAN) && !defined(INCLUDE_PCI_AUTOCONF)
/*
 * PMC Span (DEC21150 PCI-to-PCI Bridge) Configuration Parameter Array
 *
 * This array MUST contain the parameters in the order which they will
 * be set.
 */

PMC_SPAN sysPmcSpanParm [] =
{
  {PCI_CFG_COMMAND, 2,   P2P_PMC_DISABLE},
  {PCI_CFG_STATUS,  2,   P2P_CLR_STATUS >> 16},
  {PCI_CFG_BRIDGE_CONTROL, 2, P2P_SEC_BUS_RESET},
  {PCI_CFG_CACHE_LINE_SIZE, 2, P2P_CACHE_LINE_SIZE | P2P_PRIM_LATENCY},
  {PCI_CFG_PRIMARY_BUS,     1, PCI_PRIMARY_BUS},
  {PCI_CFG_SECONDARY_BUS,   1, PCI_SECONDARY_BUS},
  {PCI_CFG_SUBORDINATE_BUS, 1, PCI_SUBORD_BUS},
  {PCI_CFG_SEC_STATUS, 2,   P2P_CLR_STATUS >> 16},
  {PCI_CFG_IO_BASE, 2,   ((P2P_IO_BASE & 0x0000F000) >> 8) |
                         ((P2P_IO_BASE + P2P_IO_SIZE - 1) & 0x0000F000)},
  {PCI_CFG_MEM_BASE, 2,  ((P2P_NONPREF_MEM_BASE & 0xFFF00000) >> 16)},
  {PCI_CFG_MEM_LIMIT, 2, ((P2P_NONPREF_MEM_BASE + P2P_NONPREF_MEM_SIZE - 1) & \
                          0xFFF00000) >> 16},
  {PCI_CFG_PRE_MEM_BASE, 2, ((P2P_PREF_MEM_BASE & 0xFFF00000) >> 16)},
  {PCI_CFG_PRE_MEM_LIMIT, 2, ((P2P_PREF_MEM_BASE + P2P_PREF_MEM_SIZE - 1) & \
                              0xFFF00000) >> 16},
  {PCI_CFG_PRE_MEM_BASE_U,  4, P2P_PREF_HI32_BASE},  /* only < 4GB space */
  {PCI_CFG_PRE_MEM_LIMIT_U, 4, P2P_PREF_HI32_BASE},
  {PCI_CFG_IO_BASE_U,  2, ((P2P_IO_BASE & 0xFFFF0000) >> 16)},
  {PCI_CFG_IO_LIMIT_U, 2, ((P2P_IO_BASE + P2P_IO_SIZE - 1) & 0xFFFF0000) >> 16},
  {PCI_CFG_BRIDGE_CONTROL, 2, 0},
  {PCI_CFG_DEC21150_SEC_CLK,   2, P2P_CLK_ENABLE},
  {PCI_CFG_DEC21150_SERR_STAT, 1, (P2P_CLR_STATUS >> 16) & 0xFF},
  {PCI_CFG_STATUS,  2,  P2P_CLR_STATUS >> 16},
  {PCI_CFG_COMMAND, 2,  P2P_PMC_ENABLE}
};

#define NUM_PMC_SPAN_PARMS      (sizeof(sysPmcSpanParm) / sizeof(PMC_SPAN))
#ifdef APS_BSP
LOCAL STATUS sysPmcSpanConfig (int, int, int, PMC_SPAN *);
#endif /* APS_BSP */
#endif /* INCLUDE_PMC_SPAN) & !INCLUDE_PCI_AUTOCONF */

/* locals */

LOCAL char sysModelStr[80];
LOCAL char wrongCpuMsg[] = WRONG_CPU_MSG; 

/* forward declarations */

void    sysSpuriousIntHandler(void);
#ifndef APS_BSP
void    sysCpuCheck (void);
#else /* APS_BSP */
LOCAL   void sysCpuCheck(void);
#endif /* APS_BSP */
char *  sysPhysMemTop (void);
void sysDec21x40UpdateLoadStr (void);
UCHAR   sysNvRead(ULONG);
void    sysNvWrite(ULONG,UCHAR);
void    sysBusTasClear (volatile char *);
#ifndef APS_BSP
#if defined(INCLUDE_PMC_SPAN) && !defined(INCLUDE_PCI_AUTOCONF)
STATUS  sysPmcSpanConfig (int, int, int, PMC_SPAN *);
#endif /* INCLUDE_PMC_SPAN & !INCLUDE_PCI_AUTOCONF */
STATUS  sysBusProbe (char *, int, int, char *);
IMPORT UINT sysHid1Get(void);
#else /* APS_BSP */
LOCAL   STATUS sysBusProbe(char *, int, int, char *);
#endif /* APS_BSP */
LOCAL   BOOL sysVmeVownTas(char *);
LOCAL   BOOL sysVmeRmwTas(char *);
#ifdef APS_BSP
LOCAL   void sysVmeVownClear (volatile char *);
#endif /* APS_BSP */
void    sysDebugMsg(char * str, UINT32  recovery);
#ifndef APS_BSP
STATUS  sysAtuInit();                   /* initialize Kahlua ATU */
UINT    sysGetBusSpd(void);             /* system bus speed (in megahertz) */
UINT    sysGetBusSpdHertz(void);        /* system bus speed (in hertz) */
UINT    sysGetMpuSpd(void);             /* processor speed (in megahertz) */
UINT    sysGetMpuSpdHertz(void);        /* processor speed (in hertz) */
UINT    sysGetPciSpd(void);             /* pci bus speed (in megahertz) */
UINT    sysGetPciSpdHertz(void);        /* pci bus speed (in hertz) */
#else /* APS_BSP */
LOCAL   STATUS sysAtuInit();            /* initialize Kahlua ATU */
UINT    sysGetBusSpd(void);             /* system bus speed (in hertz) */
UINT    sysGetMpuSpd(void);             /* processor speed (in hertz) */
UINT    sysGetPciSpd(void);             /* pci bus speed (in hertz) */
#endif /* APS_BSP */

/* externals */

IMPORT UCHAR  sysInByte (ULONG);
IMPORT void   sysOutByte (ULONG, UCHAR);
IMPORT USHORT sysInWord (ULONG);
IMPORT void   sysOutWord (ULONG, USHORT);
IMPORT ULONG  sysInLong (ULONG);
IMPORT void   sysOutLong (ULONG, ULONG);
IMPORT UINT32 sysPciInLong (UINT32);
IMPORT void   sysPciOutLong (UINT32, UINT32);
IMPORT UINT32 sysPciConfigInLong (UINT32 *);
IMPORT void   sysPciConfigOutLong (UINT32 *, UINT32);
IMPORT UINT16 sysPciConfigInWord (UINT16 *);
IMPORT void   sysPciConfigOutWord (UINT16 *, UINT16);
#ifdef APS_BSP
IMPORT UINT8  sysPciConfigInByte (UINT8 *);
IMPORT void   sysPciConfigOutByte (UINT8 *, UINT8);
#endif /* APS_BSP */
IMPORT void   sysClkIntCIO (void);
IMPORT STATUS sysMemProbeSup (int length, char * src, char * dest);
IMPORT int    sysProbeExc();
IMPORT VOIDFUNCPTR      smUtilTasClearRtn;
IMPORT void   sysBusRmwEnable(UINT, UINT, UINT, char *);
IMPORT void   sysBusRmwDisable(void);
IMPORT UINT32 sysTimeBaseLGet (void);
#ifdef APS_BSP
IMPORT UINT   sysHid1Get(void);
#endif /* APS_BSP */
IMPORT UCHAR  sysProductStr[];
IMPORT UINT32 sysMemParamConfig();
#ifdef APS_BSP
IMPORT int    excExcHandle(ESFPPC *pEsf);
#endif /* APS_BSP */

/* BSP DRIVERS */

#include "pci/pciConfigLib.c"
#include "./sysEnd.c"
#include "sysSerial.c"
#include "mem/byteNvRam.c"
#include "sysMotVpd.c"
#include "timer/ppcDecTimer.c"          /* PPC603 has on chip timers */

#ifdef INCLUDE_SHOW_ROUTINES
#include "pci/pciConfigShow.c"          /* display of PCI config space */
#include "sysMotVpdShow.c"
#endif

#ifdef INCLUDE_SCSI
#   include "sysScsi.c"                 /* sysScsiInit routine */
#endif /* INCLUDE_SCSI */

#include "universe.c"
#include "kahluaEpic.c"

#ifdef INCLUDE_AUXCLK
#    include "kahluaAuxClk.c"
#endif

#ifdef INCLUDE_PCI_AUTOCONF
#  include "pci/pciAutoConfigLib.c"
#  include "./sysBusPci.c"
#endif

/* defines for sysBusTas() and sysBusTasClear() */

#define VMEBUS_OWNER    (*UNIVERSE_MAST_CTL & LONGSWAP(MAST_CTL_VOWN_ACK))
#define CPU_CLOCKS_PER_LOOP     10
#define LOCK_TIMEOUT            10
#define UNLOCK_TIMEOUT          10000

#ifdef APS_BSP
/* defines for sysA24MapRam() */
#endif /* APS_BSP */

#ifdef APS_BSP
#define MEM_PART_OVERHEAD 64


#endif /* APS_BSP */
/******************************************************************************
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.  The returned string
* depends on the board model and CPU version being used, for example,
* "Motorola MVME2600 - MPC 604e".
*
* RETURNS: A pointer to the string.
*/

char * sysModel (void)
    {
    int    cpu;
    char cpuStr[80];

    /* Determine CPU type and build display string */

    cpu = CPU_TYPE;
    switch (cpu)
        {
        case CPU_TYPE_603EK:
            sprintf(cpuStr, "8240");
            break;
        default:
            sprintf (cpuStr, "60%d", cpu);
            break;
        }

    sprintf (sysModelStr, "Motorola MVME2100 - MPC %s", cpuStr);

    return (sysModelStr);
    }

/*******************************************************************************
*
* sysBspRev - return the BSP version and revision number
*
* This routine returns a pointer to a BSP version and revision number, for
* example, 1.1/0. BSP_REV is concatenated to BSP_VERSION and returned.
*
* RETURNS: A pointer to the BSP version/revision string.
*/

char * sysBspRev (void)
    {
    return (BSP_VERSION BSP_REV);
    }

void sysDecDelay
    (
    UINT usDelay
    )
    {
    UINT  oneUsDelta;
    UINT  valueCurrent, valuePrevious, valueDelta;


    /* if no delay count, exit */

    if (!usDelay) 
        return;

    /*
     * calculate delta of decrementer ticks for 1ms of elapsed time,
     * the bus clock (in megahertz) is used for 603/604 versions, the
     * decrementer counts down once every for bus clocks for the
     * 603/604 versions, and once every RTC tick for the 601, the RTC
     * tick for 601 is the period of 1ns
     */

    oneUsDelta = ((DEC_CLOCK_FREQ / 4) / 1000000);

    /*
     * snapshot current decrementer count, this count is used
     * as the starting point
     *
     * check for rollover, the decrementer counts down from
     * the maximum count (0xffffffff) to zero
     *
     * calculate delta of the decrementer counts and divide
     * down by the one MS divider, exit if count has been
     * met or exceeded
     */

    for (valuePrevious = vxDecGet();;) 
        {
        valueCurrent = vxDecGet();
        valueDelta = 0;
        if (valueCurrent > valuePrevious) 
            {
            valueDelta = (0xFFFFFFFF - valueCurrent) + valuePrevious;
            } 
        else 
            {
            if (valueCurrent < valuePrevious) 
                {
                valueDelta = valuePrevious - valueCurrent;
                }
            }

        if ((valueDelta / oneUsDelta) >= usDelay) 
            break;
        }
    }

/******************************************************************************
*
* sysHwInit - initialize the system hardware
*
* This routine initializes various features of the CPU board.  It is called
* by usrInit() in usrConfig.c.  This routine sets up the control registers
* and initializes various devices if they are present.
*
* NOTE: This routine should not be called directly by the user application.  It
* cannot be used to initialize interrupt vectors.
*
* RETURNS: N/A
*/

void sysHwInit (void)
    {
    int         pciBusNo;       /* PCI bus number */
    int         pciDevNo;       /* PCI device number */
    int         pciFuncNo;      /* PCI function number */

    /* Initialize the VPD information */

    (void) sysVpdInit ();


    /*
     *  Validate CPU type
     */
    sysCpuCheck();

    /*
     *  Initialize PCI driver library.
     */
    if (pciConfigLibInit (PCI_MECHANISM_1, PCI_MSTR_PRIMARY_CAR, 
        PCI_MSTR_PRIMARY_CDR, 0) != OK)
        {
        sysToMonitor (BOOT_NO_AUTOBOOT);
        }

#ifdef INCLUDE_PCI_AUTOCONF
    /* Auto-Configure the PCI busses/devices. */

    /*
     * Test to determine if we need to configure the PCI busses with
     * sysPciAutoConfig().  If we are coming up from a ROM-based image
     * then we need to reconfigure.  If we have been booted from a ROM
     * image then we don't need to reconfigure since the bootrom will
     * already have reconfigured the PCI busses.  We must avoid
     * configuring the PCI busses twice on startup.
     */

    if ( !PCI_AUTOCONFIG_DONE )
        {

        /* in ROM boot phase, OK to continue and configure PCI busses.*/

        sysPciAutoConfig ();
        PCI_AUTOCONFIG_FLAG++;  /* Remember that PCI is configured */

        }
#endif

    sysDec21x40UpdateLoadStr ();

    /*
     * Do the necessary setup for the UNIVERSE chip.
     * 
     * In all cases we need to get the Base Address for the UNIVERSE
     * registers in PCI space.
     * If PCI autoconfiguration is not enabled, then we need to manually
     * configure the UNIVERSE chip.
     */

    if (pciFindDevice ((PCI_ID_UNIVERSE & 0xFFFF),
                        (PCI_ID_UNIVERSE >> 16) & 0xFFFF, 0,
                        &pciBusNo, &pciDevNo, &pciFuncNo) != ERROR)
        {
        pciToVmeDev = UNIVERSE_II;

#if !defined(INCLUDE_PCI_AUTOCONF)
        (void)pciDevConfig (pciBusNo, pciDevNo, pciFuncNo,
                            NULL,
                            PCI_MEM_UNIVERSE_ADRS,
                            (PCI_CMD_MASTER_ENABLE | PCI_CMD_MEM_ENABLE));
#endif /* !defined(INCLUDE_PCI_AUTOCONF) */

        /* get the base address for the Universe registers */

        (void)pciConfigInLong(pciBusNo, pciDevNo, pciFuncNo,
                        PCI_CFG_BASE_ADDRESS_0,
                        &univBaseAdrs);
        if (univBaseAdrs & PCI_BAR_SPACE_IO)
            {
            univBaseAdrs = (ISA_MSTR_IO_LOCAL + (univBaseAdrs & 
                            PCI_IOBASE_MASK));
            }
        else
            {
            univBaseAdrs = (PCI_MSTR_MEMIO_LOCAL + (univBaseAdrs & 
                            PCI_MEMBASE_MASK));
            }
        }

#if defined(INCLUDE_NETWORK) && !defined(INCLUDE_PCI_AUTOCONF)

    /*  Initialize the Standard PCI Header of the LANCE device if present */

    if ((pciFindDevice ((PCI_ID_PRI_LAN & 0xFFFF),
                            (PCI_ID_PRI_LAN >> 16) & 0xFFFF, 0,
                            &pciBusNo, &pciDevNo, &pciFuncNo) != ERROR))
            {
            (void)pciDevConfig (pciBusNo, pciDevNo, pciFuncNo,
                                PCI_IO_LN_ADRS,
                                NULL,
                                (PCI_CMD_MASTER_ENABLE | PCI_CMD_IO_ENABLE));
            }
        else
            {
            sysToMonitor (BOOT_NO_AUTOBOOT);
            }
#endif /* INCLUDE_NETWORK & !INCLUDE_PCI_AUTOCONF */
 
    /* initialize the address translation unit (ATU) */
 
    sysAtuInit();

    /* Initialize the EPIC. */

    sysEpicInit();

#if defined(INCLUDE_PMC_SPAN) && !defined(INCLUDE_PCI_AUTOCONF)

    /*
     * Initialize and configure PMC Span (bridge) to secondary PCI bus.
     */

    if  (pciFindDevice ((PCI_ID_BR_DEC21150 & 0xFFFF),
                        (PCI_ID_BR_DEC21150 >> 16) & 0xFFFF, 0,
                        &pciBusNo, &pciDevNo, &pciFuncNo) != ERROR)
        {
        (void)sysPmcSpanConfig (pciBusNo, pciDevNo, pciFuncNo, sysPmcSpanParm);
        }
#endif  /* INCLUDE_PMC_SPAN & !INCLUDE_PCI_AUTOCONF */

    /*
     *  The LANCE has a real driver associated with it, so
     *  no additional initialization is done here.  It's done
     *  at kernel init time.
     */

    /*
     *  Initialize the non-PCI Config Space registers of the
     *  Universe which doesn't have a true device driver.
     */

    sysUniverseInit();
 
#ifdef  INCLUDE_VME_DMA

    /*  Initialize the VMEbus DMA driver */

    sysVmeDmaInit();

#endif  /* INCLUDE_VME_DMA */

    /* set shared memory TAS Clear routine pointer */

    smUtilTasClearRtn = (VOIDFUNCPTR)sysBusTasClear;

    /* set pointer to bus probing hook */

    _func_vxMemProbeHook = (FUNCPTR)sysBusProbe;

    /* Initialize COM1 and COM2 serial channels */

    sysSerialHwInit();

    /* Extract the Ethernet address out of non-volatile RAM.
     * The Motorola convention for the Ethernet address is that they only
     * save the low 3 bytes in BBRAM.  The high three bytes are the
     * manufacturers code, and Motorola software knows its own.
     * The Motorola code is 0x08003Exxx.
     */
    sysNvRamGet ((char *)lnEnetAddr, 6, ((int) BB_ENET - NV_BOOT_OFFSET));

    /* Disable the watchdog timer */

    sysNvWrite ((ULONG)WD_TIMER, 0);

    /*
     * If mmu tables are used, this is where we would dynamically
     * update the entry describing main memory, using sysPhysMemTop().
     * We must call sysPhysMemTop () at sysHwInit() time to do
     * the memory autosizing if available.
     */

    sysPhysMemTop ();


#ifdef INCLUDE_FEIEND /* DHT -SNS02-A Added */
        sys557PciInit();
#endif

#ifdef INCLUDE_GIGEND/* DHT -SNS02-A Added */
        sysGigPciInit();
#endif  /* INCLUDE_GIGEND */

    /* Upon completion, clear the Board Fail LED */

    *(UINT8 *)MV2100_SYS_STAT_REG2 &= ~MV2100_BD_FAIL;


    }


/*******************************************************************************
*
* sysPhysMemTop - get the address of the top of physical memory
*
* This routine returns the address of the first missing byte of memory,
* which indicates the top of memory.
*
* Normally, the user specifies the amount of physical memory with the
* macro LOCAL_MEM_SIZE in config.h.  BSPs that support run-time
* memory sizing do so only if the macro LOCAL_MEM_AUTOSIZE is defined.
* If not defined, then LOCAL_MEM_SIZE is assumed to be, and must be, the
* true size of physical memory.
*
* NOTE: Do no adjust LOCAL_MEM_SIZE to reserve memory for application
* use.  See sysMemTop() for more information on reserving memory.
*
* RETURNS: The address of the top of physical memory.
*
* SEE ALSO: sysMemTop()
*/

char * sysPhysMemTop (void)
    {
#ifdef LOCAL_MEM_AUTOSIZE
    sramConfigReg MemControlReg;
#endif
    static char * sysPhysMemSize = NULL;        /* ptr to top of mem + 1 */

    if (sysPhysMemSize == NULL)
        {
#ifdef LOCAL_MEM_AUTOSIZE
        /*
         * Do dynamic memory sizing.
         *
         * Since the memory controller interface has already been set to
         * control all memory, just read and interpret its DRAM Attributes
         * Register.
         */

        sysPhysMemSize = (char *)sysMemParamConfig(&MemControlReg);

        /* Adjust initial DRAM size to actual physical memory. */

        sysPhysMemDesc[1].len = (ULONG)sysPhysMemSize -
                                (ULONG)sysPhysMemDesc[1].physicalAddr;

#else /* not LOCAL_MEM_AUTOSIZE */
        /* Don't do auto-sizing, use defined constants. */

        sysPhysMemSize = (char *)(LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_SIZE);
#endif /* LOCAL_MEM_AUTOSIZE */
        }



    return sysPhysMemSize;
    }


/*******************************************************************************
*
* sysMemTop - get the address of the top of VxWorks memory
*
* This routine returns a pointer to the first byte of memory not
* controlled or used by VxWorks.
*
* The user can reserve memory space by defining the macro USER_RESERVED_MEM
* in config.h.  This routine returns the address of the reserved memory
* area.  The value of USER_RESERVED_MEM is in bytes.
*
* RETURNS: The address of the top of VxWorks memory.
*/

char * sysMemTop (void)
    {
    static char * memTop = NULL;

    if (memTop == NULL)
        {
        memTop = sysPhysMemTop () - USER_RESERVED_MEM;
#ifdef LARGE_MEMORY_HACK
/* DHT - Limit to 32M */
        if (    memTop>0x2000000)
                memTop=0x2000000;
#endif
        }

    return memTop;
    }


/******************************************************************************
*
* sysToMonitor - transfer control to the ROM monitor
*
* This routine transfers control to the ROM monitor.  Normally, it is called
* only by reboot()--which services ^X--and by bus errors at interrupt level.
* However, in some circumstances, the user may wish to introduce a
* <startType> to enable special boot ROM facilities.
*
* RETURNS: Does not return.
*/

STATUS sysToMonitor
    (
    int startType       /* parameter passed to ROM to tell it how to boot */
    )
    {
    FUNCPTR pRom = (FUNCPTR) (ROM_TEXT_ADRS + 4); /* Warm reboot */

    cacheDisable (0);           /* Disable the Instruction Cache */
    cacheDisable (1);           /* Disable the Data Cache */

#if     (CPU == PPC604)
    vxHid0Set (vxHid0Get () & ~_PPC_HID0_SIED); /* Enable Serial Instr Exec */
#endif  /* (CPU == PPC604) */

    sysUniverseReset ();        /* reset Universe chip */
    sysSerialReset ();          /* reset serial devices */

    /* Clear the MSR */

    vxMsrSet (0);

    /* Reset the EPIC */

    sysPciOutLong((UINT32)EPIC_GLOBAL_CONFIG_REG, EPIC_GC_RESET);

    /* set the Board Fail LED */

    *(UINT8 *)MV2100_SYS_STAT_REG2 |= MV2100_BD_FAIL;

    (*pRom) (startType);

    return (OK);        /* in case we ever continue from ROM monitor */
    }


#ifdef APS_BSP
/******************************************************************************
*
* sysBusErrHandler - exception handler for VME Bus errors
*
* This routine is connected to the Machine Check Exception vector by
* sysHwInit2(), and is responsible for resetting the machine status so
* subsequent Bus Errors => PCI Recieved Target-Abort generate another
* exception.  We also call the standard exception handler to suspend the
* bad task and report the approximate location to the user.
*
* RETURNS: N/A
*/

int sysBusErrHandler
    (
    ESFPPC *    pEsf            /* pointer to exception stack frame */
    )
    {
    UINT16 pciCfg = sysPciConfigInWord((UINT16 *)(CNFG_PCI_HOST_BRDG + KAHLUA_CFG_STATUS));
    if (pciCfg & (KAHLUA_PCI_RCV_MSTR_ABORT | KAHLUA_PCI_RCV_TGT_ABORT))
        {
        sysPciConfigOutWord((UINT16 *)(CNFG_PCI_HOST_BRDG + KAHLUA_CFG_STATUS), 
                            KAHLUA_PCI_RCV_MSTR_ABORT | KAHLUA_PCI_RCV_TGT_ABORT);
        excJobAdd(sysBusErrShow, 0, 0, 0, 0, 0, 0);
        }
    return excExcHandle(pEsf); /* Won't normally return */
    }

#endif /* APS_BSP */

/******************************************************************************
*
* sysHwInit2 - initialize additional system hardware
*
* This routine connects system interrupt vectors and configures any 
* required features not configured by sysHwInit().
*
* RETURNS: N/A
*/

void sysHwInit2 (void)
    {
    static BOOL configured = FALSE;

    /* Int connects for various devices */

    if (!configured)
        {

#ifdef INCLUDE_AUXCLK
        sysAuxClkInit ();
        intConnect (INUM_TO_IVEC(TIMER0_INT_VEC), sysAuxClkInt, 0);
        intEnable (TIMER0_INT_LVL);
#endif /* INCLUDE_AUXCLK */

        /* connect Vme to PCI interrupt */

        intConnect (INUM_TO_IVEC(UNIV_INT_VEC), sysUnivVmeIntr, 0);

        /* interrupts can only be turned on ultimately by the PIC int ctrlr */

        intEnable (UNIV_INT_LVL);

        /* initialize serial interrupts */

        sysSerialHwInit2();

#ifdef APS_BSP
        /* Make VME Bus Errors generate a Machine Check exception */
        
        excVecSet((FUNCPTR *) _EXC_OFF_MACH, sysBusErrHandler);
        excVecSet((FUNCPTR *) _EXC_OFF_DATA, sysBusErrHandler);

        {
        UINT32 picr1;
        picr1 = sysPciConfigInLong((UINT32 *)(CNFG_PCI_HOST_BRDG + KAHLUA_CFG_PROC_IF_CFG1));
        picr1 |= KAHLUA_PIC1_MCP_EN;
        sysPciConfigOutLong((UINT32 *)(CNFG_PCI_HOST_BRDG + KAHLUA_CFG_PROC_IF_CFG1), picr1);
        }

        {
        UINT8 ErrEnR2;
        ErrEnR2 = sysPciConfigInByte((UINT8 *)(CNFG_PCI_HOST_BRDG + KAHLUA_CFG_ERROR_ENABLE2));
        ErrEnR2 |= KAHLUA_EE2_PCI_TARG_ABORT;
        sysPciConfigOutByte((UINT8 *)(CNFG_PCI_HOST_BRDG + KAHLUA_CFG_ERROR_ENABLE2), ErrEnR2);
        }

        sysPciConfigOutWord((UINT16 *)(CNFG_PCI_HOST_BRDG + KAHLUA_CFG_STATUS), 
                            KAHLUA_PCI_RCV_MSTR_ABORT | KAHLUA_PCI_RCV_TGT_ABORT);

        /* Enable Machine Check exceptions */

        vxMsrSet(vxMsrGet() | _PPC_MSR_ME);
        vxHid0Set(vxHid0Get() | _PPC_HID0_EMCP);

#endif /* APS_BSP */
        configured = TRUE;
        }


    }


/******************************************************************************
*
* sysProcNumGet - get the processor number
*
* This routine returns the processor number for the CPU board, which is
* set with sysProcNumSet().
*
* RETURNS: The processor number for the CPU board.
*
* SEE ALSO: sysProcNumSet()
*/

int sysProcNumGet (void)
    {
    return (sysProcNum);
    }


/******************************************************************************
*
* sysProcNumSet - set the processor number
*
* This routine sets the processor number for the CPU board.  Processor numbers
* should be unique on a single backplane.  It also maps local resources onto
* the VMEbus.
*
* RETURNS: N/A
*
* SEE ALSO: sysProcNumGet()
*
*/

void sysProcNumSet
    (
    int         procNum                 /* processor number */
    )
    {

    /*
     *  Init global variable - this needs to be done before
     *  calling sysUniverseInit2() because it calls sysProcNumGet()
     *  via the MACRO definition.
     */
    sysProcNum = procNum;

    /*
     *  Set up the node's VME slave decoders.
     */
    sysUniverseInit2(procNum);

    }


/* miscellaneous support routines */

/******************************************************************************
*
* sysLocalToBusAdrs - convert a local address to a bus address
*
* This routine returns a VMEbus address as it would be seen on the bus.
* The local address that is passed into this routine is the address of
* the local resource as seen by the CPU.
*
* RETURNS: OK, or ERROR if the address space is unknown or the mapping is not
* possible.
*
* #ifndef APS_BSP
* SEE ALSO: sysBusToLocalAdrs()
* #else APS_BSP
* SEE ALSO: sysBusToLocalAdrs(), sysVmeMapShow()
* #endif  APS_BSP 
*/
 
STATUS sysLocalToBusAdrs
    (
    int         adrsSpace,      /* bus address space where busAdrs resides */
    char *      localAdrs,      /* local address to convert */ 
    char **     pBusAdrs        /* where to return bus address */ 
    )
    {

#ifdef APS_BSP
    /* only cpu #0 maps memory to bus */
    if (sysProcNumGet () != 0)
        return ERROR;

#endif /* APS_BSP */
    switch (adrsSpace)
        {
        case VME_AM_EXT_SUP_PGM:
        case VME_AM_EXT_SUP_DATA:
        case VME_AM_EXT_USR_PGM:
        case VME_AM_EXT_USR_DATA:
#ifndef APS_BSP
            if ((VME_A32_SLV_SIZE != 0) &&
                ((ULONG)localAdrs >= VME_A32_SLV_LOCAL) &&
#else /* APS_BSP */
            if (((ULONG)localAdrs >= VME_A32_SLV_LOCAL) &&
#endif /* APS_BSP */
                ((ULONG)localAdrs < (VME_A32_SLV_LOCAL + VME_A32_SLV_SIZE)))
                {
                *pBusAdrs = localAdrs + (VME_A32_SLV_BUS - VME_A32_SLV_LOCAL);
                return (OK);
                }
#ifndef APS_BSP

            else
#endif /* APS_BSP */
                return (ERROR);

        case VME_AM_STD_SUP_PGM:
        case VME_AM_STD_SUP_DATA:
        case VME_AM_STD_USR_PGM:
        case VME_AM_STD_USR_DATA:
#ifndef APS_BSP
            if ((VME_A24_SLV_SIZE != 0) &&
                ((ULONG)localAdrs >= VME_A24_SLV_LOCAL) &&
                ((ULONG)localAdrs < (VME_A24_SLV_LOCAL + VME_A24_SLV_SIZE)))
#else /* APS_BSP */
            if ((a24memPartId != 0) &&
                ((ULONG)localAdrs >= a24memBase) &&
                ((ULONG)localAdrs < a24memBound))
#endif /* APS_BSP */
                {
#ifndef APS_BSP
                *pBusAdrs = localAdrs + (VME_A24_SLV_BUS - VME_A24_SLV_LOCAL);
#else /* APS_BSP */
                *pBusAdrs = localAdrs - a24adrOffset;
#endif /* APS_BSP */
                return (OK);
                }
#ifndef APS_BSP
            else
#endif /* APS_BSP */
                return (ERROR);

#ifndef APS_BSP
        case VME_AM_SUP_SHORT_IO:
        case VME_AM_USR_SHORT_IO:
            if ((VME_A16_SLV_SIZE != 0) &&
                ((ULONG)localAdrs >= VME_A16_SLV_LOCAL) &&
                ((ULONG)localAdrs < (VME_A16_SLV_LOCAL + VME_A16_SLV_SIZE)))
                {
                *pBusAdrs = localAdrs + (VME_A16_SLV_BUS - VME_A16_SLV_LOCAL);
                return (OK);
                }
            else
                return (ERROR);
 
#else /* APS_BSP */
#if (VME_A16_SLV_SIZE != 0)
        case VME_AM_SUP_SHORT_IO:
        case VME_AM_USR_SHORT_IO:
            if (((ULONG)localAdrs >= VME_A16_SLV_LOCAL) &&
                ((ULONG)localAdrs < (VME_A16_SLV_LOCAL + VME_A16_SLV_SIZE)))
                {
                *pBusAdrs = localAdrs + (VME_A16_SLV_BUS - VME_A16_SLV_LOCAL);
                return (OK);
                }
            return (ERROR);
#endif /* VME_A16_SLV_SIZE */ 
#endif /* APS_BSP */
        default:
            return (ERROR);
        }
    }

/************************************************************************/
/* DHT@SNS - Rewrote entire function */

STATUS sysBusToLocalAdrs
    (
    int         adrsSpace,      /* bus address space where busAdrs resides */
    char *      busAdrs,        /* bus address to convert */
    char **     pLocalAdrs      /* where to return local address */
    )
    {

    unsigned int * univ_ctl[8];
    char * base, * bound;
    unsigned long offset, ctl;
    int i;
    unsigned long VAS;

#define VAS_MASK LSI_CTL_USER2

    univ_ctl[0]=UNIVERSE_LSI0_CTL;
    univ_ctl[1]=UNIVERSE_LSI1_CTL;
    univ_ctl[2]=UNIVERSE_LSI2_CTL;
    univ_ctl[3]=UNIVERSE_LSI3_CTL;
    univ_ctl[4]=UNIVERSE_LSI4_CTL;
    univ_ctl[5]=UNIVERSE_LSI5_CTL;
    univ_ctl[6]=UNIVERSE_LSI6_CTL;
    univ_ctl[7]=UNIVERSE_LSI7_CTL;
    

    switch (adrsSpace)
        {
        case VME_AM_EXT_SUP_PGM:
        case VME_AM_EXT_USR_PGM:
        case VME_AM_EXT_SUP_DATA:
        case VME_AM_EXT_USR_DATA:
                VAS=LSI_CTL_A32;
                break;
        case VME_AM_STD_SUP_PGM:
        case VME_AM_STD_USR_PGM:
        case VME_AM_STD_SUP_DATA:
        case VME_AM_STD_USR_DATA:
                VAS=LSI_CTL_A24;
                break;
        case VME_AM_SUP_SHORT_IO:
        case VME_AM_USR_SHORT_IO:
                VAS=LSI_CTL_A16;
                break;
        default:
            return (ERROR);
        }
        for (i=0;i<8;i++)
        {
                UNIV_IN_LONG(univ_ctl[i],&ctl);
                if ((ctl&VAS_MASK)==VAS)
                {
                        UNIV_IN_LONG(univ_ctl[i]+1,&base);
                        UNIV_IN_LONG(univ_ctl[i]+2,&bound);
                        UNIV_IN_LONG(univ_ctl[i]+3,&offset);
                        if (busAdrs >= (base+offset) && busAdrs < (bound+offset))
                        {
                                *pLocalAdrs= busAdrs-offset;
                                return OK;
                        }
                }
        
        
        }
        return ERROR;
    }


/*====*/
/*******************************************************************************
*
* sysBusTas - test and set a specified location
*
* #ifndef APS_BSP
* This routine performs a test-and-set (TAS) instruction on the specified
* address.  To prevent deadlocks, interrupts are disabled during the
* test-and-set operation.  The following table defines the method used to
* insure an atomic operation.
* #else APS_BSP
* This routine performs an atomic test-and-set (TAS) instruction on 
* the specified byte address.  One of three different methods is used
* depending on where the TAS location is and the SM_OFF_BOARD macro.
* sysVmeRmwTas is used for all off-board locations, and vxTas for
* locations within vxWorks' SM_MEM boundaries as long as the
* SM_OFF_BOARD macro is FALSE.sysVmeVownTas is used for all other
* conditions.
* #endif  APS_BSP
*
* #ifndef APS_BSP
* .CS
*               Master          Slave_1         Slave_2
*#else  APS_BSP
* RETURNS: TRUE if the value had not been set but is now
*          FALSE if the value was already set.
* #endif APS_BSP
*
*#ifndef APS_BSP
* VME Chip      Don't Care      U1              U1
*               ----------      ----            ----
* Method        VOWN            VOWN            VOWN
*
* VME Chip      Don't Care      U1              U2
*               ----------      ----            ----
* Method        VOWN            VOWN            RMW
*
* VME Chip      U1 or           U2              U2
*               U2+
*               ----------      ----            ----
* Method        VOWN+++         RMW             RMW
*
* VME Chip      U2++            U2              U2
* PCI Bridge    or Raven3
*               ----------      ----            ----
* Method        lwarx/stwcx     RMW             RMW
*
*  +   = Refer to target.txt file for explanation of older boards
*        with Universe II (U2).
*  ++  = Refer to target.txt file for explanation of newer boards
*        with Universe II (U2).
*  +++ = The master's hardware does not preserve the atomic RMW.
* ++++ = If SM_OFF_BOARD == TRUE,  the method used will be the same
*        as if the master board is acting like a slave board; namely:
*               RMW for UNIVERSE_II and VOWN for UNIVERSE_I
* .CE
*
* NOTE: Although the address passed-in to sysBusTas() is defined as
* "char *", vxTas() operates on the address as a "void *".
* For PowerPC, this implies that the location tested-and-set is
* actually a 32-bit entity.
* 
* RETURNS: TRUE if the value had not been set but is now, or
* FALSE if the value was set already.
*
* #endif APS_BSP
* SEE ALSO: vxTas(), sysBusTasClear()
*/
#ifndef APS_BSP
BOOL sysBusTas
    (
    char * adrs          /* address to be tested and set */
    )
    {
    /* Check for master node */

    if (sysProcNumGet() == 0)
        {
#ifdef  ANY_BRDS_IN_CHASSIS_NOT_RMW

        /*
         * A slave board in the chassis cannot generate a VMEbus RMW,
         * and/or the master board cannot translate an incoming VMEbus
         * RMW into an atomic operation, and/or the master board cannot
         * generate a VMEbus RMW; therefore, the master must set
         * VOWN before doing a TAS.
         */

        return (sysVmeVownTas(adrs));

#else
#if     (SM_OFF_BOARD == FALSE)
        BOOL state = FALSE;  /* semaphore state */
        int  lockKey;        /* interrupt lock key */

        /* 
         * All slave boards in the chassis are generating a VMEbus RMW, and
         * the master board can translate an incoming VMEbus RMW into an
         * atomic operation; therefore, the master can simply call vxTas()
         * (lwarx/stwcx sequence) because the write portion of the RMW will
         * be detected.
         */

        /* lock interrupts so that vxTas() can execute without preemption */

        lockKey = intLock ();

        /* Perform TAS on local address */

        state =  vxTas ((UINT *)adrs);
        SYNC;

        intUnlock (lockKey);

        /* return TAS test result */

        return (state);

#else
        /* The master board can generate a VMEbus RMW */

        return (sysVmeRmwTas(adrs));

#endif  /* SM_OFF_BOARD */

#endif  /* ANY_BRDS_IN_CHASSIS_NOT_RMW */
        }
    else        /* Slave node */
        {
        if (pciToVmeDev == UNIVERSE_II)
            {
            /* A board with the UNIVERSE_II can generate a VMEbus RMW */

            return (sysVmeRmwTas(adrs));
                }
        else    /* UNIVERSE_I */
            {
            /*
             * A slave board with the UNIVERSE_I cannot generate a VMEbus
             * RMW; therefore, it must set VOWN before doing a TAS.
             */

            return (sysVmeVownTas(adrs));

            }
        }

    }

#else /* APS_BSP */

BOOL sysBusTas
    (
    char * adrs          /* address to be tested and set */
    )
    {
    if (IS_VME_ADDRESS(adrs))
        {
        return (sysVmeRmwTas(adrs));
        }

#if (SM_OFF_BOARD == FALSE)
    else if ((adrs >= (char *) SM_MEM_ADRS) && 
             (adrs < (char *) SM_MEM_ADRS + SM_MEM_SIZE + SM_OBJ_MEM_SIZE))
        {
        /* use vxTas */

        BOOL state = FALSE;  /* semaphore state */
        int  lockKey;        /* interrupt lock key */

        /* lock interrupts so that vxTas() can execute without preemption */

        lockKey = intLock ();

        /* Perform TAS on local address */

        state =  vxTas ((UINT *)adrs);
        SYNC;

        intUnlock (lockKey);

        /* return TAS test result */

        return (state);

        }
#endif /* (SM_OFF_BOARD == FALSE) */

    /* Got to grab the VMEbus first */
    return (sysVmeVownTas(adrs));
    }



#endif /* APS_BSP */

/******************************************************************************
*
* sysBusTasClear - clear a location set by sysBusTas()
*
* #ifndef APS_BSP
* This routine clears the specified 32-bit location typically set
* by sysBusTas().  The following table defines the method used to
* insure an atomic operation.
* #else APS_BSP
* This routine clears the specified test-and-set location typically set
* by sysBusTas().  One of three methods is used depending on where the
* TAS location is and the SM_OFF_BOARD macro.
* #endif APS_BSP
*
* #ifndef APS_BSP
* .CS
*               Master          Slave_1         Slave_2
*
* VME Chip      Don't Care      U1              U1
*               ----------      ----            ----
* Method        VOWN            VOWN            VOWN
*
* VME Chip      Don't Care      U1              U2
*               ----------      ----            ----
* Method        VOWN            VOWN            RMW
*
* VME Chip      U1 or           U2              U2
*               U2+
*               ----------      ----            ----
* Method        VOWN+++         RMW             RMW
*
* VME Chip      U2++            U2              U2
* PCI Bridge    or Raven3
*               ------------    ------------    ------------
* Method        simple clear    simple clear    simple clear
*
*
*  +   = Refer to target.txt file for explaination of older boards
*        with Universe II (U2).
*  ++  = Refer to target.txt file for explaination of newer boards
*        with Universe II (U2).
*  +++ = The master's hardware does not preserve the atomic RMW.
* ++++ = If SM_OFF_BOARD == TRUE,  no special/additional processing
*        is required.
* .CE
*
* #endif  APS_BSP
* RETURNS: N/A
*
* SEE ALSO: sysBusTas()
*/
#ifndef APS_BSP

void sysBusTasClear
    (
    volatile char * adrs        /* Address of semaphore to be cleared */
    )
    {

#ifdef  ANY_BRDS_IN_CHASSIS_NOT_RMW

    /*
     * A slave board in the chassis cannot generate a VMEbus RMW,
     * and/or the master board cannot translate an incoming VMEbus
     * RMW into an atomic operation; therefore, the master must set
     * VOWN before clearing a local TAS location.
     */

    BOOL state;
    int  lockKey;        /* interrupt lock key */

    /* Check for master node or slave node with UNIVERSE_I */

    if ((sysProcNumGet() == 0) ||
        (pciToVmeDev == UNIVERSE_I))
        {

        /*
         * Compute a 10 microsecond delay count
         *
         * NotTimeOut(loops) = timeout(usec)/clks/loop/CPU_SPEED(clks/usec)
         */

        int  NotTimeOut = ((MEMORY_BUS_SPEED/1000000) * UNLOCK_TIMEOUT)
                            / CPU_CLOCKS_PER_LOOP;

        /* do clearing with no interference */

        lockKey = intLock ();

        /* request ownership of the VMEbus */

        *UNIVERSE_MAST_CTL |= LONGSWAP(MAST_CTL_VOWN);
        SYNC;

        /* wait for the VME controller to give you the BUS */

        while (!VMEBUS_OWNER && NotTimeOut)
            {
            --NotTimeOut;
            }

        /* clear the location */

        *(UINT *)adrs = 0;
        SYNC;

        /* release the VME BUS */

        *UNIVERSE_MAST_CTL &= LONGSWAP(~MAST_CTL_VOWN);

        /* enable normal operation */

        intUnlock (lockKey);
        }
    else        /* Slave node == UNIVERSE_II */
        {
        /* Lock interrupts so that setting up SCG and issuing RMW are atomic */

        lockKey = intLock ();

        /* Enable RMW cycle */

        sysBusRmwEnable(VME_SCG_COMPARE_MASK,
                        VME_SCG_COMPARE_TO_CLEAR,
                        VME_SCG_SWAP_TO_CLEAR,
                        (char *)adrs);

        /* perform RMW to clear TAS location */

        state = *((UINT *)adrs);
        SYNC;

        /* Disable RMW cycle */

        sysBusRmwDisable();

        /* unlock the interrupt */

        intUnlock (lockKey);
        }
#else
#if     (SM_OFF_BOARD == FALSE)
    /*
     * All slave boards in the chassis can generate a VMEbus RMW, and
     * the master board can translate an incoming VMEbus RMW into an
     * atomic operation therefore, all boards can do a simple clear.
     */

    *(UINT *)adrs = 0;
    SYNC;

#else   /* SM_OFF_BOARD == TRUE */

    /* Check for master node or slave node with UNIVERSE_I */

    if ((sysProcNumGet() == 0) ||
        (pciToVmeDev == UNIVERSE_I))
        {
        /*
         * Compute a 10 microsecond delay count
         *
         * NotTimeOut(loops) = timeout(usec)/clks/loop/CPU_SPEED(clks/usec)
         */

        int  NotTimeOut = ((MEMORY_BUS_SPEED/1000000) * UNLOCK_TIMEOUT)
                            / CPU_CLOCKS_PER_LOOP;

        /* do clearing with no interference */

        lockKey = intLock ();

        /* request ownership of the VMEbus */

        *UNIVERSE_MAST_CTL |= LONGSWAP(MAST_CTL_VOWN);
        SYNC;

        /* wait for the VME controller to give you the BUS */

        while (!VMEBUS_OWNER && NotTimeOut)
            {
            --NotTimeOut;
            }

        /* clear the location */

        *(UINT *)adrs = 0;
        SYNC;

        /* release the VME BUS */

        *UNIVERSE_MAST_CTL &= LONGSWAP(~MAST_CTL_VOWN);

        /* enable normal operation */

        intUnlock (lockKey);
        }
    else        /* Slave node == UNIVERSE_II */
        {
        /* Lock interrupts so that setting up SCG and issuing RMW are atomic */

        lockKey = intLock ();

        /* Enable RMW cycle */

        sysBusRmwEnable(VME_SCG_COMPARE_MASK,
                        VME_SCG_COMPARE_TO_CLEAR,
                        VME_SCG_SWAP_TO_CLEAR,
                        (char *)adrs);

        /* perform RMW to clear TAS location */

        state = *((UINT *)adrs);
        SYNC;

        /* Disable RMW cycle */

        sysBusRmwDisable();

        /* unlock the interrupt */

        intUnlock (lockKey);
        }

#endif  /* SM_OFF_BOARD */
#endif  /* ANY_BRDS_IN_CHASSIS_NOT_RMW */
    }



#else /* APS_BSP */
void sysBusTasClear
    (
    volatile char * adrs        /* Address of semaphore to be cleared */
    )
    {
    /* Check for an off-board location */
    
    if (IS_VME_ADDRESS(adrs))
        {
        /* Use a simple clear, 8 bits only */
        SYNC;
        *adrs = 0;
        }
#if (SM_OFF_BOARD == FALSE)
    else if ((adrs >= (char *) SM_MEM_ADRS) && 
             (adrs < (char *) SM_MEM_ADRS + SM_MEM_SIZE + SM_OBJ_MEM_SIZE))
        {
        /* Use a simple clear, 32-bits */
        SYNC;
        *(UINT *)adrs = 0;
        }
#endif
    else
        {
        /* Got to grab the VMEbus first */
        sysVmeVownClear(adrs);
        }
    }




#endif /* APS_BSP */




/*******************************************************************************
*
* sysVmeVownTas - test and set a location across the VMEbus
*
* This routine performs a test-and-set (TAS) instruction on the specified
* address.  To prevent deadlocks, interrupts are disabled and the VMEbus is
* locked during the test-and-set operation.  sysVmeVownTas can be used with
* local or VME locations, but in both cases the atomicity of its operation
* is maintained by retaining ownership of the VMEbus between two separate
* test and set instructions.  This will not be atomic where a competing CPU
* has a non-VMEbus route to the location, unless that CPU still claims the
* VMEbus around its test-and-set operation like sysVmeVownTas does even
* when the address is local to the mv2100 CPU.
*
* NOTE: Although the address passed in to sysBusTas() is defined as "char *",
* the vxTas() argument is a "void *".  For PowerPC the location that is
* tested-and-set using sysVmeVownTas is therefor a 32-bit entity.
* 
* RETURNS: TRUE if the value had not been set but is now
* FALSE if the VMEbus cannot be locked or the value was already set.
*
* SEE ALSO: vxTas(), sysVmeVownTasClear(), sysVmeRmwTas()
*/

#ifndef APS_BSP
LOCAL BOOL sysVmeVownTas
    (
    char * adrs          /* address to be tested and set */
    )
    {
    BOOL state = FALSE;  /* semaphore state */
    int  lockKey;        /* interrupt lock key */

    /*
     * Compute a 10 microsecond delay count
     *
     * NotTimeOut(loops) = timeout(usec)/clks/loop/CPU_SPEED(clks/usec)
     */

    int  NotTimeOut = ((MEMORY_BUS_SPEED/1000000) * LOCK_TIMEOUT)
                        / CPU_CLOCKS_PER_LOOP;

    /* lock interrupts so there will be no TAS interference */

    lockKey = intLock ();

    /* Request ownership of the VMEbus */

    *UNIVERSE_MAST_CTL |= LONGSWAP(MAST_CTL_VOWN);
    SYNC;

    /* Wait for the VME controller to give you the BUS */

    while (!VMEBUS_OWNER && NotTimeOut)
        {
        --NotTimeOut;
        }

    /* perform the TAS */

    if (VMEBUS_OWNER)
        {
        state =  vxTas ((UINT *)adrs);
        SYNC;
        }

    /* release the VME BUS */
    
    *UNIVERSE_MAST_CTL &= LONGSWAP(~MAST_CTL_VOWN);

    /* unlock the interrupt */

    intUnlock (lockKey);

    /* return TAS test result */

    return (state);

    }
#else /* APS_BSP */
LOCAL BOOL sysVmeVownTas
    (
    char * adrs          /* address to be tested and set */
    )
    {
    BOOL state = FALSE;  /* semaphore state */
    int  lockKey;        /* interrupt lock key */

    /*
     * Compute a 10 microsecond delay count
     *
     * NotTimeOut(loops) = timeout(usec)/clks/loop/CPU_SPEED(clks/usec)
     */

    int  NotTimeOut = ((MEMORY_BUS_SPEED/1000000) * LOCK_TIMEOUT)
                        / CPU_CLOCKS_PER_LOOP;

    /* lock interrupts so there will be no TAS interference */

    lockKey = intLock ();

    /* Request ownership of the VMEbus */

    *UNIVERSE_MAST_CTL |= LONGSWAP(MAST_CTL_VOWN);
    SYNC;

    /* Wait for the VME controller to give you the BUS */

    while (!VMEBUS_OWNER && NotTimeOut)
        {
        --NotTimeOut;
        }

    /* perform the TAS */

    if (VMEBUS_OWNER)
        {
        state =  vxTas ((UINT *)adrs);
        SYNC;
        }

    /* release the VME BUS */
    
    *UNIVERSE_MAST_CTL &= LONGSWAP(~MAST_CTL_VOWN);

    /* unlock the interrupt */

    intUnlock (lockKey);

    /* return TAS test result */

    return (state);

    }


#endif /* APS_BSP */

#ifdef APS_BSP


/*******************************************************************************
*
* sysVmeVownClear - clear a test-and-set location
*
* This routine clears a test-and-set (TAS) word at the specified address.
* To prevent deadlocks, interrupts are disabled and the VMEbus is locked
* during the clear operation.  sysVmeVownClr can be used with local or
* VME locations, but is only actually needed for addresses local to the
* mv2700 where a remote CPU is using sysVmeVownTas for its test-and-set
* method.  This prevents the mv2700 clear from happening in between the
* test and set cycles from the remote CPU.  Deadlock would occur if the
* other CPU always did the write operation even when the test failed.
*
* NOTE: Although the address passed in to sysBusTas() is defined as "char *",
* the vxTas() argument is a "void *".  For PowerPC the location that is
* tested-and-set using sysVmeVownTas is therefor a 32-bit entity.
* 
* RETURNS: TRUE if the value had not been set but is now
* FALSE if the VMEbus cannot be locked or the value was already set.
*
* SEE ALSO: vxTas(), sysVmeRmwTas
*/

LOCAL void sysVmeVownClear
    (
    volatile char * adrs          /* address that was tested and set */
    )
    {
    int  lockKey;        /* interrupt lock key */

    /*
     * Compute a 10 microsecond delay count
     *
     * NotTimeOut(loops) = timeout(usec)/clks/loop/CPU_SPEED(clks/usec)
     */

    int  NotTimeOut = ((MEMORY_BUS_SPEED/1000000) * LOCK_TIMEOUT)
                        / CPU_CLOCKS_PER_LOOP;

    /* lock interrupts to prevent interference */

    lockKey = intLock ();

    /* Request ownership of the VMEbus */

    *UNIVERSE_MAST_CTL |= LONGSWAP(MAST_CTL_VOWN);
    SYNC;

    /* Wait for the VME controller to give you the BUS */

    while (!VMEBUS_OWNER && NotTimeOut)
        {
        --NotTimeOut;
        }

    /* clear the location anyway */

    SYNC;
    *(UINT *)adrs = 0;

    /* release the VME BUS */

    *UNIVERSE_MAST_CTL &= LONGSWAP(~MAST_CTL_VOWN);

    /* unlock the interrupt */

    intUnlock (lockKey);

    }
#endif /* APS_BSP */



/*******************************************************************************
*
* sysVmeRmwTas - test and set a location across the VMEbus utilizing RMW
*
* This routine performs a test-and-set (TAS) instruction on the specified
* #ifndef APS_BSP
* address.  To prevent deadlocks, interrupts are disabled and the VMEbus is
* locked during the test-and-set operation.
* #else APS_BSP 
* address, which must be on a different VME board.  Interrupts are disabled 
* during the test-and-set operation so the Universe II chip's Special Cycle 
* Generator is only enabled for the RMW operation.  sysVmeRmwTas can only
* test-and-set locations across the VMEbus, local addresses may be tested
* but never set.
* #endif  APS_BSP 
*
* #ifndef APS_BSP
* NOTE: Although the address passed-in to sysBusTas() is defined as
*       "char *", vxTas() operates on the address as a "void *".
*       For PowerPC, this implies that the location tested-and-set is
*       actually a 32-bit entity.
* #else APS_BSP 
* NOTE: Unlike the built-in vxTas() routine from vxWorks, this version
* of sysVmeRmwTas provides full emulation of the MC680x0's TAS instruction
* by only accessing the byte pointed to, and only altering the top bit of
* that byte.  The two are compatible as long as the same 4-byte aligned
* address is used.
* #endif  APS_BSP 
* 
* RETURNS: TRUE if the value had not been set but is now
* #ifndef APS_BSP
*          FALSE if the VMEbus cannot be locked or the value was already set.
* #else APS_BSP 
* FALSE if the value was already set.
* #endif APS_BSP 
*
* #ifndef APS_BSP
* SEE ALSO: vxTas()
* #else  APS_BSP 
* SEE ALSO: vxTas(), sysVmeVownTas()
* #endif  APS_BSP 
*/

#ifndef APS_BSP
LOCAL BOOL sysVmeRmwTas
    (
    char * adrs          /* address to be tested and set */
    )
    {
    BOOL state = FALSE;  /* semaphore state */
    int  lockKey;        /* interrupt lock key */

    /* A board with the UNIVERSE_II can generate a VMEbus RMW */

    /*
     * Lock interrupts so that setting up SCG and issuing RMW
     * are atomic
     */

    lockKey = intLock ();

    /* Enable RMW cycle */

    sysBusRmwEnable(VME_SCG_COMPARE_MASK,
                    VME_SCG_COMPARE_TO_SET,
                    VME_SCG_SWAP_TO_SET,
                    (char *)adrs);

    /* perform RMW to try and set TAS location */

    state = *((UINT *)adrs);
    SYNC;

    /* Disable RMW cycle */

    sysBusRmwDisable();

    /* unlock the interrupt */

    intUnlock (lockKey);

    /* return TAS test result */

    if (state)
        {
        return (FALSE);
        }
    else
        {
        return (TRUE);
        }
    }

#else /* APS_BSP */
LOCAL BOOL sysVmeRmwTas
    (
    char * adrs          /* address to be tested and set */
    )
    {
    BOOL state = FALSE;  /* semaphore state */
    int  lockKey;        /* interrupt lock key */
    ULONG mask = 0x80000000 >> ((ULONG) adrs & 0x3) * 8; /* bit to TAS */

    /* A board with the UNIVERSE_II can generate a VMEbus RMW */

    /*
     * Lock interrupts so that setting up SCG and issuing RMW
     * are atomic
     */

    lockKey = intLock ();

    /* Enable RMW cycle */

    sysBusRmwEnable (mask, 0x00000000, 0x80808080, adrs);

    /* perform RMW to try and set TAS location */

    state = *adrs;
    SYNC;

    /* Disable RMW cycle */

    sysBusRmwDisable();

    /* unlock the interrupt */

    intUnlock (lockKey);

    /* return TAS test result */

    return (state & 0x80) ? (FALSE) : (TRUE);
    }
#endif /* APS_BSP */


/******************************************************************************
*
* sysLanIntEnable - enable the LAN interrupt
*
* This routine enables interrupts at a specified level for the on-board LAN
* chip.  The LANCE chip on this board is on the Peripheral Component
* Interconnect (PCI) bus.  The LANCE chip asserts PCI IRQ0 which is routed
* to the EPIC Serial Interrupt #1.
*
* RETURNS: OK, or ERROR if network support not included.
*
* SEE ALSO: sysLanIntDisable()
*/

STATUS sysLanIntEnable
    (
    int intLevel                /* interrupt level to enable */
    )
    {
#ifdef INCLUDE_NETWORK
    intEnable (intLevel);
    return (OK);
#else
    return (ERROR);
#endif /* INCLUDE_NETWORK */
    }


/******************************************************************************
*
* sysLanIntDisable - disable the LAN interrupt
*
* This routine disables interrupts for the on-board LAN chip. 
*
* RETURNS: OK, or ERROR if network support not included.
*
* SEE ALSO: sysLanIntEnable()
*/

STATUS sysLanIntDisable
    (
    int intLevel                /* interrupt level to enable */
    )
    {
#ifdef INCLUDE_NETWORK
    /* 
     *  disable the Serial interrupt #1 for the MV2100
     */

    intDisable (intLevel);

    return (OK);
#else
    return (ERROR);
#endif /* INCLUDE_NETWORK */
    }


/******************************************************************************
*
* sysSpuriousIntHandler - spurious interrupt handler
*
* This is the entry point for spurious interrupts.
*
* NOTE: This routine has no effect.
*
* This routine catches all spurious interrupts.  It does nothing at all.
*
* RETURNS: N/A.
*
* RETURNS: N/A
*
* NOMANUAL
*/

void sysSpuriousIntHandler (void)
    {
    }


/******************************************************************************
*
* sysNvRead - read one byte from NVRAM
*
* This routine reads a single byte from a specified offset in NVRAM.
*
* RETURNS: The byte from the specified NVRAM offset.
*/

UCHAR sysNvRead
    (
    ULONG       offset  /* NVRAM offset to read the byte from */
    )
    {
    return (sysInByte (NVRAM_BASE + offset));
    }


/******************************************************************************
*
* sysNvWrite - write one byte to NVRAM
*
* This routine writes a single byte to a specified offset in NVRAM.
*
* RETURNS: N/A
*/

void sysNvWrite
    (
    ULONG       offset, /* NVRAM offset to write the byte to */
    UCHAR       data    /* datum byte */
    )
    {
    sysOutByte (NVRAM_BASE + offset, data);
    }


/*******************************************************************************
*
* sysCpuCheck - confirm the CPU type
*
* This routine validates the cpu type.  If the wrong cpu type is discovered
* a message is printed using the serial channel in polled mode.
*
* RETURNS: N/A.
*/

#ifdef APS_BSP
LOCAL
#endif /* APS_BSP */
void sysCpuCheck (void)
    {
    int msgSize;
    int msgIx;
    SIO_CHAN * pSioChan;        /* serial I/O channel */

    /* Check for a valid CPU type;  If one is found, just return */

    if  ((CPU_TYPE == CPU_TYPE_603) || (CPU_TYPE == CPU_TYPE_603E) ||
         (CPU_TYPE == CPU_TYPE_603P) || (CPU_TYPE == CPU_TYPE_603EK))
        {
        return;
        }

    /* Invalid CPU type; print error message and terminate */

    msgSize = strlen (wrongCpuMsg);

    sysSerialHwInit ();

    pSioChan = sysSerialChanGet (0);

    sioIoctl (pSioChan, SIO_MODE_SET, (void *) SIO_MODE_POLL);

    for (msgIx = 0; msgIx < msgSize; msgIx++)
        {
        while (sioPollOutput (pSioChan, wrongCpuMsg[msgIx]) == EAGAIN);
        }

    sysToMonitor (BOOT_NO_AUTOBOOT);
    }


#if defined(INCLUDE_PMC_SPAN) && !defined(INCLUDE_PCI_AUTOCONF)
/******************************************************************************
*
* sysPmcSpanConfig - configure the PMC Span (DEC21150 PCI-to-PCI Bridge)
*
* This routine configures the DEC21150 PCI-to-PCI Bridge on the PMC Span.
*
* RETURNS: OK or ERROR if pciConfigLib has not been initialized.
*/

#ifdef APS_BSP
LOCAL
#endif /* APS_BSP */
STATUS sysPmcSpanConfig
    (
    int         pciBusNo,       /* PCI bus number */
    int         pciDevNo,       /* PCI device number */
    int         pciFuncNo,      /* PCI function number */
    PMC_SPAN *  pmcSpan         /* pointer to PMC Span config array */
    )
    {
    STATUS      result = OK;
    FAST        i;

    /* Write all parameters in pcmSpan in the order given */

    for (i = 0; i < NUM_PMC_SPAN_PARMS && result == OK; ++i)
        {
        switch (pmcSpan[i].parmSize)
            {
            case 1:
                result = pciConfigOutByte (pciBusNo, pciDevNo, pciFuncNo,
                                           pmcSpan[i].parmOffset,
                                           pmcSpan[i].parmValue);
                break;

            case 2:
                result = pciConfigOutWord (pciBusNo, pciDevNo, pciFuncNo,
                                           pmcSpan[i].parmOffset,
                                           pmcSpan[i].parmValue);
                break;

            case 4:
                result = pciConfigOutLong (pciBusNo, pciDevNo, pciFuncNo,
                                           pmcSpan[i].parmOffset,
                                           pmcSpan[i].parmValue);
                break;
            }
        }

    return (result);
    }
#endif /* INCLUDE_PMC_SPAN  & !defined(INCLUDE_PCI_AUTOCONF) */


/******************************************************************************
*
* sysMemProbeTrap - trap handler for vxMemProbe exception
*
* This routine is called from the excConnectCode stub if sysMemProbeSup
* generates an exception. By default, sysMemProbeSup returns OK.
* This code changes the PC value to "sysProbeExc" (within the sysMemProbeSup
* routine), and sysProbeExc sets the return value to ERROR.
*
* RETURNS: 0
*/

static int sysMemProbeTrap
    (
    ESFPPC *    pEsf            /* pointer to exception stack frame */
    )
    {
    REG_SET *pRegSet = &pEsf->regSet;

    pRegSet->pc = (_RType)sysProbeExc;  /* sysProbeExc forces an ERROR return */
    return (0);
    }


/******************************************************************************
*
* sysMemProbeBus - probe an address on a bus.
*
* This routine probes a specified address to see if it is readable or
* writable, as specified by <mode>.  The address will be read or written as
* 1, 2, or 4 bytes as specified by <length> (values other than 1, 2, or 4
* yield unpredictable results).  If the probe is a VX_READ, the value read will
* be copied to the location pointed to by <pVal>.  If the probe is a VX_WRITE,
* the value written will be taken from the location pointed to by <pVal>.
* In either case, <pVal> should point to a value of 1, 2, or 4 bytes, as
* specified by <length>.
*
* This routine probes the specified address with interrupts disabled and
* a special handler for Machine Check, Data Access and Alignment exceptions.
*
* RETURNS: OK if probe succeeded or ERROR if an exception occured.
*/

static STATUS sysMemProbeBus
    (
    char   * adrs,      /* address to be probed */
    int      mode,      /* VX_READ or VX_WRITE */
    int      length,    /* 1, 2 or 4 byte probe */
    char   * pVal       /* address of value to write OR */
                        /* address of location to place value read */
    )
    {
    int      oldLevel;
    FUNCPTR  oldVec1;
    FUNCPTR  oldVec2;
    STATUS   status;
    UINT32   ppcHid0;   /* H/W Implementation Dependent reg (PPC60x) */
    UINT32   ppcMsr;    /* PPC Machine Status Reg */
    UINT16   temp;

    /* Probes performed with interrupts disabled */

    oldLevel = intLock ();

    /* Handle Machine Check Exceptions locally */

    oldVec1 = excVecGet ((FUNCPTR *) _EXC_OFF_MACH);
    excVecSet ((FUNCPTR *) _EXC_OFF_MACH, FUNCREF(sysMemProbeTrap)); 

    /*
     *  Handle Data Access Exceptions locally
     *
     *  Data Access Exceptions will occur when trying to probe addresses
     *  that have not been mapped by the MMU.
     */

    oldVec2 = excVecGet ((FUNCPTR *) _EXC_OFF_DATA);
    excVecSet ((FUNCPTR *) _EXC_OFF_DATA, FUNCREF(sysMemProbeTrap));

    /* Enable Machine Check Pin (EMCP) */

    ppcHid0 = vxHid0Get();
    vxHid0Set(ppcHid0 | _PPC_HID0_EMCP);

    /* Enable Machine Check exception */

    ppcMsr = vxMsrGet();
    vxMsrSet(ppcMsr | _PPC_MSR_ME);

    /* clear the PCI abort bits in the PCI status word */

    sysPciConfigOutWord((UINT16 *)(CNFG_PCI_HOST_BRDG + KAHLUA_CFG_STATUS),
                        (KAHLUA_PCI_RCV_MSTR_ABORT | KAHLUA_PCI_RCV_TGT_ABORT));

    /* do probe */

    if (mode == VX_READ)
        {
        status = sysMemProbeSup (length, adrs, pVal);
        SYNC;
        }
    else
        {
        status = sysMemProbeSup (length, pVal, adrs);
        SYNC;
        }

    /* check for valid address */

    temp = sysPciConfigInWord((UINT16 *)(CNFG_PCI_HOST_BRDG + 
                              KAHLUA_CFG_STATUS));
    if (temp & (KAHLUA_PCI_RCV_MSTR_ABORT | KAHLUA_PCI_RCV_TGT_ABORT))
        status = ERROR;

    /* clear the PCI status reg. bits */

    sysPciConfigOutWord((UINT16 *)(CNFG_PCI_HOST_BRDG + KAHLUA_CFG_STATUS), 
                        (KAHLUA_PCI_RCV_MSTR_ABORT | KAHLUA_PCI_RCV_TGT_ABORT));

    /* Disable Machine Check Exceptions */

    vxMsrSet(ppcMsr);

    /* Disable Machine Check Pin (EMCP) */

    vxHid0Set(ppcHid0);

    /* restore original vectors and unlock */

    excVecSet ((FUNCPTR *) _EXC_OFF_DATA, oldVec2);

    excVecSet ((FUNCPTR *) _EXC_OFF_MACH, oldVec1);

    intUnlock (oldLevel);

    return (status);
    }


/******************************************************************************
*
* sysProbeErrClr - clear errors associated with probing an address on a bus.
*
* This routine clears the error flags and conditions in the DAR, DSISR, SRR0
* and SRR1 PowerPC registers arising from probing addresses as well as the
* PCI_CFG_STATUS registers and the Universe PCI_CSR and V_AMERR registers.
*
* RETURNS: N/A
*/

void sysProbeErrClr (void)
    {
    UINT32  pciCsr;

    /* Get current status */

    pciCsr = sysPciInLong ((UINT32)(UNIVERSE_PCI_CSR));

    /* Clear PCI_CSR */

    sysPciOutLong ((UINT32)(UNIVERSE_PCI_CSR), pciCsr);

    /* Clear any VME address error */

    sysPciOutLong ((UINT32)UNIVERSE_V_AMERR, V_AMERR_V_STAT);

    /* Force write due to Write-Posting and get updated status */

    pciCsr = sysPciInLong ((UINT32)(UNIVERSE_PCI_CSR));

    /* Clear PowerPC Data Access Exception Registers */

    vxDarSet   (0);
    vxDsisrSet (0);
    vxSrr0Set  (0);
    vxSrr1Set  (0);
    }

/******************************************************************************
*
* sysVmeProbe - probe a VME bus address
*
* This routine probes an address on the VME bus.  The PCI bridge chip
* must have a special setup to enable generation of Master Abort cycles on
* write probes and reception of Target Abort cycles on read probes.
* The CPU must be configured to enable Machine Check exceptions.  In 
* addition, if the probe is a write, the Universe must be configured to
* disable Posted Writes.  All probing is done with interrupts disabled.
*
* NOTE: This routine assumes that the Universe Local Control registers are
* dedicated to these VME address spaces:
*
* .CS
* #ifndef APS_BSP
*   LSI0 - LM/SIG (mailbox)
* #endif  APS_BSP 
*   LSI1 - A32
*   LSI2 - A24
*   LSI3 - A16
* .CE
*
* RETURNS: OK or ERROR if address cannot be probed
*/

#ifndef APS_BSP
STATUS sysVmeProbe
#else /* APS_BSP */
LOCAL STATUS sysVmeProbe
#endif /* APS_BSP */
    (
    char   * adrs,      /* address to be probed */
    int      mode,      /* VX_READ or VX_WRITE */
    int      length,    /* 1, 2 or 4 byte probe */
    char   * pVal       /* address of value to write OR */
                        /* address of location to place value read */
    )
    {
    STATUS status = ERROR;
    UINT32 lsiCtlReg;   /* adress of Local Control register in Universe */
    UINT32 pciSlv1Ctl;  /* Universe PCI Slave Image Control reg */

    /* Determine which Control register controls this address */

#ifndef APS_BSP
    if ((VME_LM_MSTR_SIZE != 0) && ((UINT32)adrs >= VME_LM_MSTR_BUS) &&
        ((UINT32)adrs <= (VME_LM_MSTR_BUS + VME_LM_MSTR_SIZE)))
        lsiCtlReg = (UINT32)(UNIVERSE_LSI0_CTL);
    else
#endif /* APS_BSP */
    if ((VME_A32_MSTR_SIZE != 0) && ((UINT32)adrs >= VME_A32_MSTR_LOCAL) &&
             ((UINT32)adrs <= (VME_A32_MSTR_LOCAL + VME_A32_MSTR_SIZE)))
        lsiCtlReg = (UINT32)(UNIVERSE_LSI1_CTL);
    else if ((VME_A24_MSTR_SIZE != 0) && ((UINT32)adrs >= VME_A24_MSTR_LOCAL) &&
             ((UINT32)adrs <= (VME_A24_MSTR_LOCAL + VME_A24_MSTR_SIZE)))
        lsiCtlReg = (UINT32)(UNIVERSE_LSI2_CTL);
    else if ((VME_A16_MSTR_SIZE != 0) && ((UINT32)adrs >= VME_A16_MSTR_LOCAL) &&
             ((UINT32)adrs <= (VME_A16_MSTR_LOCAL + VME_A16_MSTR_SIZE)))
        lsiCtlReg = (UINT32)(UNIVERSE_LSI3_CTL);
    else
        return (ERROR);

    /* If write probe, disable Posted Writes in Universe */

    pciSlv1Ctl = sysPciInLong (lsiCtlReg);
    if (mode == VX_WRITE)
        {
        sysPciOutLong (lsiCtlReg, (pciSlv1Ctl & ~LSI_CTL_WP));
        }

    /* Perform probe */

    status = sysMemProbeBus (adrs, mode, length, pVal);

    /* Restore Posted Writes by Universe if previously enabled */

    if ((mode == VX_WRITE) && (pciSlv1Ctl & LSI_CTL_WP))
        {
        sysPciOutLong (lsiCtlReg, pciSlv1Ctl);
        }

    return (status);
    }


/******************************************************************************
*
* sysPciProbe - probe a PCI bus address
*
* This routine probes an address on the PCI bus.  The PCI bridge chip
* must have a special setup to enable generation of Master Abort cycles on
* write probes and reception of Target Abort cycles on read probes.
* The CPU must be configured to enable Machine Check exceptions.  In 
* addition, if the probe is a write, the Universe must be configured to
* disable Posted Writes.  All probing is done with interrupts disabled.
*
* RETURNS: OK or ERROR if address cannot be probed
*/

#ifndef APS_BSP
STATUS sysPciProbe
#else /* APS_BSP */
LOCAL STATUS sysPciProbe
#endif /* APS_BSP */
    (
    char   * adrs,      /* address to be probed */
    int      mode,      /* VX_READ or VX_WRITE */
    int      length,    /* 1, 2 or 4 byte probe */
    char   * pVal       /* address of value to write OR */
                        /* address of location to place value read */
    )
    {
    STATUS status = ERROR;

    /* Perform probe */

    status = sysMemProbeBus (adrs, mode, length, pVal);

    return (status);
    }


/******************************************************************************
*
* sysBusProbe - probe a bus address based on bus type.
*
* This routine is a function hook into vxMemProbe.  It determines which bus,
* VME, PCI or local is being probed based on the address to be probed.
* If the VME bus is being probed, the sysVmeProbe() routine is called to do
* the special VME probing.  If the PCI bus is being probed, the sysPciProbe()
* routine is called to do the special PCI probing.  If the local bus is being
* probed, the routine returns ERROR which indicates that the default local
* bus probe in vxMemProbe() should be used.
*
* RETURNS: ERROR if local bus is being probed, OK if VME or PCI bus.
*/

#ifndef APS_BSP
STATUS  sysBusProbe
#else /* APS_BSP */
LOCAL STATUS sysBusProbe
#endif /* APS_BSP */
    (
    char   * adrs,      /* address to be probed */
    int      mode,      /* VX_READ or VX_WRITE */
    int      length,    /* 1, 2 or 4 byte probe */
    char   * pVal       /* address of value to write OR */
                        /* address of location to place value read */
    )
    {
    STATUS status;

    /* Clear any existing errors/exceptions */

    sysProbeErrClr ();

    /* Handle VME bus in special manner */

    if (IS_VME_ADDRESS(adrs))
        status = sysVmeProbe (adrs, mode, length, pVal);

    /* Handle PCI bus in special manner */

    else if (IS_PCI_ADDRESS(adrs))
        status = sysPciProbe (adrs, mode, length, pVal);

    /* Handle local bus in architecture-specific manner */

    else
        status = vxMemArchProbe (adrs, mode, length, pVal);

    /* Clear any errors/exceptions before exiting */

    sysProbeErrClr ();

    return (status);
    }

#ifndef APS_BSP
/******************************************************************************
*
* sysUsDelay - delay at least the specified amount of time (in microseconds)
*
* This routine will delay for at least the specified amount of time using the
* lower 32 bit "word" of the Time Base register as the timer.  The accuracy of
* the delay increases as the requested delay increases due to a certain amount
* of overhead.  As an example, a requested delay of 10 microseconds is
* accurate within approximately twenty percent, and a requested delay of 100
* microseconds is accurate within approximately two percent.
*
* NOTE:  This routine will not relinquish the CPU; it is meant to perform a
* busy loop delay.  The minimum delay that this routine will provide is
* approximately 10 microseconds.  The maximum delay is approximately the
* size of UINT32; however, there is no roll-over compensation for the total
* delay time, so it is necessary to back off two times the system tick rate
* from the maximum.
*
* RETURNS: N/A
*/


void sysUsDelay
    (
    UINT32      delay           /* length of time in microsec to delay */
    )
    {
    register UINT baselineTickCount;
    register UINT curTickCount;
    register UINT terminalTickCount;
    register int actualRollover = 0;
    register int calcRollover = 0;
    UINT ticksToWait;
    UINT requestedDelay;
    UINT oneUsDelay;

    /* Exit if no delay count */

    if ((requestedDelay = delay) == 0)
        return;

    /*
     * Get the Time Base Lower register tick count, this will be used
     * as the baseline.
     */

    baselineTickCount = sysTimeBaseLGet();

    /*
     * Calculate number of ticks equal to 1 microsecond
     *
     * The Time Base register and the Decrementer count at the same rate:
     * once per 4 System Bus cycles.
     *
     * e.g., 66666666 cycles     1 tick      1 second             16 tick
     *       ---------------  *  ------   *  --------          =  ----------
     *       second              4 cycles    1000000 microsec    microsec
     */

    oneUsDelay = ((DEC_CLOCK_FREQ / 4) / 1000000);

    /* Convert delay time into ticks */

    ticksToWait = requestedDelay * oneUsDelay;

    /* Compute when to stop */

    terminalTickCount = baselineTickCount + ticksToWait;

    /* Check for expected rollover */

    if (terminalTickCount < baselineTickCount)
        {
        calcRollover = 1;
        }

    do
        {
        /*
         * Get current Time Base Lower register count.
         * The Time Base counts UP from 0 to
         * all F's.
         */

        curTickCount = sysTimeBaseLGet();

        /* Check for actual rollover */

        if (curTickCount < baselineTickCount)
            {
            actualRollover = 1;
            }

        if (((curTickCount >= terminalTickCount)
            && (actualRollover == calcRollover)) ||
            ((curTickCount < terminalTickCount)
            && (actualRollover > calcRollover)))
            {
            /* Delay time met */

            break;
            }

        }
    while (TRUE); /* Breaks when delay time is met */
    }

#endif /* APS_BSP */
/******************************************************************************
*
* sysDebugMsg - print a debug string to the console in polled mode.
*
* This routine prints a message to the system console in polled mode and
* optionally exits to the monitor.
*
* RETURNS: N/A
*
*/

void sysDebugMsg
    (
    char * str,
    UINT32  recovery
    )
    {
    int msgSize;
    int msgIx;
    SIO_CHAN * pSioChan;        /* serial I/O channel */

    msgSize = strlen (str);

    sysSerialHwInit ();

    pSioChan = sysSerialChanGet (0);

    sioIoctl (pSioChan, SIO_MODE_SET, (void *) SIO_MODE_POLL);

    for (msgIx = 0; msgIx < msgSize; msgIx++)
        {
        while (sioPollOutput (pSioChan, str[msgIx]) == EAGAIN);
        }

    /* follow caller's error recovery policy. */

#ifdef DEBUGMSG_RECOVERY
    if (recovery == EXIT_TO_SYSTEM_MONITOR)
        sysToMonitor (BOOT_NO_AUTOBOOT);
#endif
    }

#if defined(INCLUDE_NETWORK)
/*****************************************************************************
* sysDynEnetFind - Find ethernet network device dynamically
*
* This function dynamically finds the ethernet network device.  The
* encoded location is returned the 'pciLoc' output parameter if the
* device is found.  The constraints of the search require that the
* device found be on the PCI bus number which matches the 'bus' input
* parameter.  In addition, if the 'unit' input parameter is zero, the
* device/vendor ID must match the PCI_ID_PRI_LAN define.
*
* RETURNS: OK if ethernet device is found, ERROR otherwise
*/

STATUS sysDynEnetFind
    (
    int       unit,             /* input: unit number */
    UINT      bus,              /* input: bus number on which to look */
    PCI_LOC * pciLoc            /* output: encoded location of device */
    )
    {

    UINT    findClass;
    UINT    pciBus;
    UINT    pciDevice;
    UINT    pciFunc;
    UINT    devVend;
    UINT    index = 0;
    STATUS  status = ERROR;

    findClass = (UINT)((PCI_CLASS_NETWORK_CTLR << 16)  |
                      (PCI_SUBCLASS_NET_ETHERNET << 8) |
                      (0 << 0) /* Prog I/F = 0 */
                      );

    while (pciFindClass(findClass, index,
           &pciBus, &pciDevice, &pciFunc) == OK)
        {
        if (pciBus == bus)
            {
            pciConfigInLong (pciBus, pciDevice, pciFunc,
                             PCI_CFG_VENDOR_ID, &devVend);

            if ( ((unit == 0) && (devVend == PCI_ID_PRI_LAN)) )
                {
                pciLoc->bus = pciBus;
                pciLoc->device = pciDevice;
                pciLoc->function = pciFunc;
                status = OK;
                break;
                }
            }
        index++;
        }
    return (status);
    }
#endif /* defined(INCLUDE_NETWORK) */

#if defined(INCLUDE_PCI_AUTOCONF) && !defined(INCLUDE_END)
/*****************************************************************************
*
* sysDynDcAttach - Dynamically attach ethernet driver
*
* This function dynamically attaches the network driver to the actual PCI
* network hardware via a 'dcattach()' function call.  It works in
* conjunction with the two macros: NETIF_USR_DECL and NETIF_USR_ENTRIES
* defined in "config.h".  The presence of these two macros causes
* usrNetIfAttach() to call this function 'sysDynDcAttach()' directly
* instead of calling 'dcattach()' directly.  This function dynamically
* determines the CPU memory address, interrupt vector and interrupt
* level parameters (associated with the dummy arguments: dummmyDevAdrs,
* dummyIvec, dummyIlevel) by using information read from the already
* configured PCI configuration header for this device.  The "unit"
* argument is used to discern between primary ethernet (unit == 0) and
* secondary ethernet (unit == 1).  Only network devices which reside on
* bus 0 are attached.  Also the primary/secondary specification of the
* "unit" parameter causes this function to check the device/vendor field
* of the PCI header.  Primary ethernet must match PCI_ID_PRI_LAN,
* otherwise dcattach() is not called and FALSE is returned.
*
* RETURNS: OK if dcattach() succeeds, ERROR if PCI header not found or
* if dcattach() fails.
*/

STATUS sysDynDcAttach
    (
    int         unit,           /* unit number */
    ULONG       dummmyDevAdrs,  /* LANCE I/O address (dummy) */
    int         dummyIvec,      /* interrupt vector (dummy) */
    int         dummyIlevel,    /* interrupt level (dummy) */
    char *      memAdrs,        /* address of memory pool (-1 = malloc it) */
    ULONG       memSize,        /* only used if memory pool is NOT malloc()'d */
    int         memWidth,       /* byte-width of data (-1 = any width) */
    ULONG       pciMemBase,     /* main memory base as seen from PCI bus */
    int         dcOpMode        /* mode of operation */
    )
    {
    IMPORT int dcattach ();

    int     index = 0;
    UINT    bar0;
    char    *cpuPciAddr;
    STATUS  status = ERROR;
    UINT    devVend;
    int     ivec;
    int     ilevel;
    UCHAR   intLine;
    UINT    pciBus, pciDevice, pciFunc;
    PCI_LOC pciList;

    while (sysDynEnetFind ( unit, index, 0, &pciList ) == OK)
        {
        pciBus = pciList.bus;
        pciDevice = pciList.device;
        pciFunc = pciList.function;

        pciConfigInLong (pciBus, pciDevice, pciFunc,
                         PCI_CFG_VENDOR_ID, &devVend);

        PCI_AUTO_DEBUG_MSG("sysDynDcAttach: found NIC [%d %d %d] dev_vend[0x%08x]\n",
                pciBus, pciDevice, pciFunc, devVend,0,0 );

        if ( (unit == 0) && (devVend == PCI_ID_PRI_LAN) )
            {

            /*
             * Dynamically compute PCI address to pass to dcattach().
             * It is computed from the already configured PCI header
             * base address 0.
             */

            pciConfigInLong(pciBus, pciDevice, pciFunc,
                            PCI_CFG_BASE_ADDRESS_0, &bar0);

            cpuPciAddr = (char *)((bar0 & 0xfffffffe) |
                                   ISA_MSTR_IO_LOCAL);

            /*
             * Dynamically compute interrupt vector 'ivec' and
             * interrupt level 'ilevel' from the already configured
             * "interrupt line" field of the PCI config header.
             */

            pciConfigInByte (pciBus, pciDevice, pciFunc,
                             PCI_CFG_DEV_INT_LINE, &intLine);

            ivec = (int)intLine;
            ilevel = (int)intLine;

            /* Do the dcattach() with the dynamiclly computed arguments. */

            PCI_AUTO_DEBUG_MSG("sysDynDcAttach: dc%d addr[0x%08x]\n", 
                               index,cpuPciAddr,0,0,0,0);
            PCI_AUTO_DEBUG_MSG("                irq[0x%08x], opmode[0x%08x]\n",
                               ilevel,dcOpMode,0,0,0,0);

            status = dcattach(index,cpuPciAddr,ivec,ilevel,memAdrs,
                              memSize,memWidth,pciMemBase,dcOpMode);

            if (status != OK)
                {
                break;
                PCI_AUTO_DEBUG_MSG("sysDynDcAttach: attach dc%d failed\n",index,0,0,0,0,0 );
                }
            }
        index++;
        }
    return(status);
    }
#endif /* defined(INCLUDE_PCI_AUTOCONF) && !defined(INCLUDE_END) */

/******************************************************************************
*
* sysAtuInit - initialize ATU
*
* This function's purpose is to initialize the address translation
* unit for use by the operating system.
*
* RETURNS: Ok always
*/

#ifndef APS_BSP
STATUS sysAtuInit (void)
#else /* APS_BSP */
LOCAL STATUS sysAtuInit (void)
#endif /* APS_BSP */
    {
    UINT32      value;

    /*
     * initialize the inbound translation window and enable it,
     * the inbound translation window permits PCI bus masters to access
     * system memory, the enable is nothing more than enabling PCI memory
     * accesses in host's bridge PCI command configuration register
     */
    sysPciOutLong( (UINT32)KAHLUA_ATU_ITWR, 0 );

    value = sysPciConfigInLong((UINT32 *)(CNFG_PCI_HOST_BRDG + 0x10));
    value = (value & 0x00000FFF) | LOCAL_MEM_LOCAL_ADRS;
    sysPciConfigOutLong((UINT32 *)(CNFG_PCI_HOST_BRDG + 0x10), value);

    value = sysPciConfigInWord((UINT16 *)(CNFG_PCI_HOST_BRDG + 0x04));
    value |= 0x0002;
    sysPciConfigOutWord((UINT16 *)(CNFG_PCI_HOST_BRDG + 0x04), value);
 
    return (OK);
    }

#ifdef APS_BSP

STATUS sysA24MapRam(unsigned long size) {
    void *a24memAlloc;
    
    if ((sysProcNumGet() != 0) ||
        (a24memPartId != NULL))
        return ERROR;
    
    if (size > 0x800000)
        size = 0x800000;                /* Maximum size is 8MB */
    else if (size < 0x010000)
        size = 0x010000;                /* Minimum size is 64KB */
    
    a24memAlloc = cacheDmaMalloc(size);
    if (a24memAlloc == NULL)
        return ERROR;
    
    a24memPartId = memPartCreate(a24memAlloc, size);
    if (a24memPartId == NULL)
        {
        cacheDmaFree(a24memAlloc);
        a24memAlloc = 0;
        return ERROR;
        }
    
    /* Got the memory, now set up the Universe chip. */
    a24memBase  = 0xffff0000 & (unsigned long) a24memAlloc;
    a24memBound = 0xffff0000 & ((unsigned long) a24memAlloc + size + 0x10000);
    /* a24vmeBase is the constant VME_A24_SLV_BUS */
    a24adrOffset = a24memBase - VME_A24_SLV_BUS;
    a24vmeBound  = a24memBound - a24adrOffset;
    
    UNIV_OUT_LONG(UNIVERSE_VSI2_BS, VME_A24_SLV_BUS);
    UNIV_OUT_LONG(UNIVERSE_VSI2_BD, a24vmeBound);
    UNIV_OUT_LONG(UNIVERSE_VSI2_TO, a24adrOffset);
    UNIV_OUT_LONG(UNIVERSE_VSI2_CTL, VAL_VSI2_CTL);
    
    return OK;
    }


void *sysA24Malloc
    (
    unsigned long size  /* number of bytes to allocate */
    )
    {
    if (a24memPartId == NULL)
        {
        /* None allocated, get enough for this request */
        if (sysA24MapRam(size + MEM_PART_OVERHEAD) != OK)
            return NULL;
        }
    
    return(memPartAlloc(a24memPartId, size));
    }


/*******************************************************************************
*
* sysA24Free - free a block of memory from the A24 partition
*
* This routine returns to the A24 partition a block of memory that was
* previously allocated with sysA24Malloc().
*
* RETURNS: OK, or ERROR if the block is invalid.
*
* SEE ALSO: sysA24MapRam(), sysA24Malloc(), sysA24MemShow()
*/

STATUS sysA24Free
    (
    char *pBlock        /* pointer to block of memory to free */
    )
    {
    if (a24memPartId == NULL)
        return ERROR;
    
    return(memPartFree(a24memPartId, pBlock));
    }


void sysA24MemShow(void)
    {
        if (a24memPartId)
            {
            memPartShow(a24memPartId, 0);
            }
        else
            puts("\nNo A24 memory currently reserved");
    }


STATUS sysVmeMapShow(void)
    {
    unsigned long base, bound, offset, ctl;
    
    printf("\nVMEbus access from CPU:\n");
    UNIV_IN_LONG(UNIVERSE_LSI1_BS, &base);
    UNIV_IN_LONG(UNIVERSE_LSI1_BD, &bound);
    UNIV_IN_LONG(UNIVERSE_LSI1_TO, &offset);
    printf("  CPU:\t0x%8.8lX - 0x%8.8lX  =>  A32: 0x%8.8lX - 0x%8.8lX\n",
           base, bound - 1, base + offset, bound + offset - 1);

    UNIV_IN_LONG(UNIVERSE_LSI2_BS, &base);
    UNIV_IN_LONG(UNIVERSE_LSI2_BD, &bound);
    UNIV_IN_LONG(UNIVERSE_LSI2_TO, &offset);
    printf("\t0x%8.8lX - 0x%8.8lX  =>  A24:   0x%6.6lX -   0x%6.6lX\n",
           base, bound - 1, (base + offset) & 0xffffff, 
           (bound + offset - 1) & 0xffffff);

    UNIV_IN_LONG(UNIVERSE_LSI3_BS, &base);
    UNIV_IN_LONG(UNIVERSE_LSI3_BD, &bound);
    UNIV_IN_LONG(UNIVERSE_LSI3_TO, &offset);
    printf("\t0x%8.8lX - 0x%8.8lX  =>  A16:     0x%4.4lX -     0x%4.4lX\n",
           base, bound - 1, (base + offset) & 0xffff, 
           (bound + offset - 1) & 0xffff);

    printf("\nCPU access from VMEbus:\n");
    UNIV_IN_LONG(UNIVERSE_VSI1_CTL, &ctl);
    if (ctl & VSI_CTL_EN)
        {
        UNIV_IN_LONG(UNIVERSE_VSI1_BS, &base);
#if ((SM_OFF_BOARD == FALSE) && !defined(ANY_BRDS_IN_CHASSIS_NOT_RMW))
        UNIV_IN_LONG(UNIVERSE_VSI5_BD, &bound);
#else
        UNIV_IN_LONG(UNIVERSE_VSI1_BD, &bound);
#endif
        UNIV_IN_LONG(UNIVERSE_VSI1_TO, &offset);
        printf("  A32:\t0x%8.8lX - 0x%8.8lX  =>  CPU: 0x%8.8lX - 0x%8.8lX\n",
                base, bound - 1, base + offset, bound + offset - 1);
        }
    else
        printf("  A32:\t           -             =>                  -\n");
    
    UNIV_IN_LONG(UNIVERSE_VSI2_CTL, &ctl);
    if (ctl & VSI_CTL_EN)
        {
        UNIV_IN_LONG(UNIVERSE_VSI2_BS, &base);
        UNIV_IN_LONG(UNIVERSE_VSI2_BD, &bound);
        UNIV_IN_LONG(UNIVERSE_VSI2_TO, &offset);
        printf("  A24:\t  0x%6.6lX -   0x%6.6lX  =>       0x%8.8lX - 0x%8.8lX\n",
                base, bound - 1, base + offset, bound + offset - 1);
        }
    
    UNIV_IN_LONG(UNIVERSE_VRAI_CTL, &ctl);
    if (ctl & VRAI_CTL_EN)
        {
        UNIV_IN_LONG(UNIVERSE_VRAI_BS, &base);
        bound = base + VME_VRAI_SLV_SIZE;
        printf("  A24:\t  0x%6.6lX -   0x%6.6lX  =>       Universe-2 Registers\n",
                base, bound - 1);
        }
    
    return OK;
    }
#endif /* APS_BSP */
static char identsysLib_c[]="@(#) $Name:  $ $Id: sysLib.c,v 1.4.2.1 2002/09/12 21:45:36 thompson Exp $";

---