for all parent regions, determining if an output of the parent region is compatible with an output of a current region of a cell,

when the output of the parent region is compatible with the output of the current region of a cell, reducing the output of the parent region taking into account the current region; or

when the output of the parent region is not compatible with the output of the current region of a cell, copying an incompatible output of a sub-region to a promote container and promoting the incompatible output to an output of all other parent regions;

generating a layout hierarchy from input data;

generating a layout hierarchy from region data, wherein the layout hierarchy from the input data and the layout hierarchy from the region data are determined using an inverse layout tree (ILT); and

determining a difference between the layout hierarchy generated from the input data and the layout hierarchy generated from the region data;

the method further comprising:

generating an empty ILT;

for all parent regions, choosing a next parent region of a current region and adding a path from a current cell to a cell-instance of the current parent region in the ILT;

checking if an ILT-node is a leaf and, if the ILT-node is a leaf, ending the recursion;

when the ILT-node is not a leaf, selecting a next parent instance of the cell and checking if there is a corresponding branch in the current ILT-Node, and if there is a corresponding branch, recursively following the corresponding ILT branch; and

when there is no corresponding branch in the current ILT-Node, generating an output of the promote containers of the current region in the parent instance;

wherein the layout can be used in the fabrication of a semiconductor device.