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The NASA/DoD Workshop on Evolvable Hardware Monday, July 19 |
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| 8:50 - 9:00 |
A. Stoica, Workshop Chair J. Koza, Honorary Chair Welcome and Organizational Remarks |
| 9:00 - 9:15 |
M. Chahine, JPL Chief Scientist, USA Welcome Address |
| 9:15 - 9:40 | W. Huntress Jr., Carnegie Institution of
Washington, USA NASA Rediscovers Technology |
| 9:30 - 10:00 |
L. Alkalai, Jet Propulsion Laboratory Micro/Nano Systems for Future NASA Grand Challenges in Deep Space Microsystems |
| 10:00 - 10:45 |
J. Muñoz, DARPA DARPA's Adaptive Computing System Program |
| 10:45 - 11:00 |
Break |
| 11:00 - 11:45 |
I. Parmee, Plymouth University, UK Identifying Requirements of Evolutionary Design Search, Exploration and Optimisation |
| 11:45 - 12:30 |
T. Higuchi, Electrotechnical Laboratory, Japan Evolvable Hardware for Industrial Applications |
| 12:30 - 1:45 |
Lunch |
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Session 1: Evolution on FPGAs Chair: J. Miller, Napier University, UK |
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| 1:45 - 2:10 |
J. Miller, Napier University, UK On the filtering properties of Evolved Gate Arrays |
| 2:10 - 2:35 |
D. Levi, S. Guccione, Xilinx Inc., USA Genetic FPGA: Evolving Stable Circuits on Mainstream FPGA Devices |
| 2:35 - 3:00 |
G. Tufte, P. Haddow, The Norwegian University of Science and Technology, Norway Prototyping a GA Pipeline for Complete Hardware Evolution |
| 3:00 - 3:25 |
E. Damiani, A. Tettamanzi, Università degli Studi di Milano, Italy; V. Liberali, Università degli Studi di Pavia, Italy On line Evolution of FPGA-based Circuits: A Case Study on Hash Functions |
| 3:25 - 3:40 |
Break |
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Session 2: Design and Adaptation of Space Subsystems Chair: R. Haupt, University of Nevada, USA |
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| 3:40 - 4:05 |
W. Crossley, Purdue University, USA Optimization for Aerospace Conceptual Design through the use of Genetic Algorithms |
| 4:05 - 4:30 |
J. Pollack, H. Lipson, P. Funes, S. Ficici, G. Hornby, Brandeis University, USA Coevolutionary Robotics |
| 4:30 - 4:55 |
R. Haupt, J. Johnson, University of Nevada, Reno, USA Dynamic Phase-Only Array Beam Control Using a Genetic Algorithm |
| 4:55 - 5:20 |
D. Linden, Linden Innovation Research LLC, USA; E. Altshuler, Air Force Research Laboratory, USA Evolving Wire Antennas using Genetic Algorithms: A Review |
| 5:20 - 5:45 |
M. Buehler, Jet Propulsion Laboratory, USA The Effects of Extreme Environments on Measurement Equipment |
| 5:45 - 6:10 |
A. Avizienis, University of California, Los Angeles, USA The Hundred Year Spacecraft |
| 7:00 - 8:30 |
Reception Athenaeum, California Institute of Technology |
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The NASA/DoD Workshop on Evolvable Hardware Tuesday, July 20 |
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| 9:00 - 9:45 |
J. Koza, Stanford University, USA Evolving Circuits by Means of Natural Selection |
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Session 3: Evolution of Analog and Mixed-Signal Circuits Chair: F. Bennett III, Genetic Programming Inc., USA |
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| 9:45 - 10:10 |
R. Zebulum, M. Pacheco, M. Vellasco, University of Sussex, UK; Centro de Inteligencia Computacional Aplicada, Brasil Artificial Evolution of Active Filters: A Case Study |
| 10:10 -10:35 |
A. Stoica, D. Keymeulen, R. Tawel, C. Salazar-Lazaro, W. Li, Jet Propulsion Laboratory, USA Evolutionary Experiments with a Fine-Grained Reconfigurable Architecture for Analog and Digital CMOS Circuits |
| 10:35 - 10:50 |
Break |
| 10:50 - 11:20 |
A. Thompson, University of Sussex, UK Explorations in Design Space: Can Evolutionary Algorithms Practically Search beyond the Scope of Conventional Electronics Design? |
| 11:20 - 11:45 |
P. Layzell, University of Sussex, UK Inherent Qualities of Circuits Designed by Artificial Evolution: A Preliminary Study of Populational Fault Tolerance |
| 11:45 - 12:10 |
J. Lohn, G. Haith, S. Colombano, D. Stassinopoulos, NASA Ames Research Center, USA A Comparison of Dynamic Fitness Schedules in Automated Amplifier Design |
| 12:10 - 12:35 |
S. Flockton, K. Sheehan, University of London, UK A System for Intrinsic Evolution of Linear and Non-linear Filters |
| 12:35 - 2:00 |
Lunch |
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Session 4: Evolution of Digital Functions Chair: A. Thompson, University of Sussex, UK |
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| 2:00 - 2:25 |
V. Vassilev, J. Miller, T. Fogarty, Napier University, UK On the Nature of Two-Bit Multiplier Landscapes |
| 2:25 - 2:50 |
A. Hernandez-Aguirre, Tulane University, USA; C. Coello, Laboratorio Nacional de Informatica Avanzada, México; B. Buckles, Tulane University, USA A Genetic Programming Approach to Logic Function Synthesis by Means of Multiplexers |
| 2:50 - 3:15 |
T. Kalganova, J. Miller, Napier University, UK Evolving More Efficient Digital Circuits by Allowing Circuit Layout Evolution and Multi-objective Fitness |
| 3:15 - 3:30 |
Break |
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Session 5: Dynamic Reconfiguration Chair: S. Casselman, Virtual Computer Corp., USA |
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| 3:30 - 3:55 |
G. Lu, H. Singh, M. Lee, N. Bagherzadeh, F. Kurdahi, University of California at Irvine, USA; E. Filho, V. Alves, COPPE/Federal University of Rio de Janeiro, Brazil The MorphoSys Dynamically Reconfigurable System-On-Chip |
| 3:55 - 4:20 |
G. Milne, University of South Australia, Australia A Model for Dynamic Adaptation in Reconfigurable Hardware System |
| 4:20 - 4:30 |
Break |
| 4:30 - 6:00 |
Panel: The Future of Reconfigurable Computing Technologies Organizer and Moderator: J. Schewel, Virtual Computer Corp. P. Athanas, Virginia Tech; S. Trimberger, Xilinx, Inc.; S. Casselman, President, Virtual Computer Corp.; D. Levi, Xilinx, Inc.; L. Alkalai, Jet Propulsion Laboratory |
| 7:00 - 9:00 |
Banquet
Speaker: D. Fogel Dusting off Some Old Evolvable Hardware |
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The NASA/DoD Workshop on Evolvable Hardware Wednesday, July 21 |
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Session 6: Evolution of Cellular Automata and Brain-Inspired Architectures I Chair: S. Colombano, NASA ARC, USA |
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| 9:00 - 9:30 |
P. Marchal, Centre Suisse d' Electronique et de Microelectronique SA (Switzerland) Embryological Electronics |
| 9:30 - 9:55 |
H. de Garis, A. Buller, M. Korkin, F. Gers, N. Nawa, M. Hough, ATR, Japan; Technical University of Gdansk, Poland; Genobyte Inc., USA; IDSIA, Switzerland; Stanford University, USA ATR's Artificial Brain (CAM-Brain) Project: A Sample of what Individual "CoDi-1Bit" Model Evolved Neural Net Modules can do with Digital and Analog I/O |
| 9:55 - 10:20 |
V. Vassilev, J. Miller, T. Fogarty, Napier University, UK Co-evolving Demes of Non-Uniform Cellular Automata for Synchronisation |
| 10:20 - 10:45 |
C. Ortega, A. Tyrrell, University of York, UK Reliability Analysis in Self-Repairing Embryonic Systems |
| 10:45 - 11:00 |
Break |
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Session 7: Evolution of Cellular Automata and Brain-Inspired Architectures II Chair: A. Thakoor, JPL, USA |
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| 11:00 - 11:20 |
M. Perkovski, Portland State University, USA; A. Chebotarev, Glushkov Institute of Cybernetics, Ukraine; A. Mishchenko, Portland State University, USA Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints |
| 11:20 - 11:40 |
E. Mjolsness, E. Meyerowitz, V. Gor, T. Mann, Jet Propulsion Laboratory, Caltech, USA Morphogenesis in Plants: Modeling the Shoot Apical Meristem, and Possible Applications |
| 11:40 - 12:00 |
P. Davis, ATR Adaptive Communications Research Laboratories, Japan Adaptive Networks with Self-Organizing Multi-Hop Links |
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Session 8: Reconfiguration Architectures Chair: A. Hunsberger, National Security Agency, USA |
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| 12:00 - 12:20 |
R. Porter, K. McCabe, Los Alamos National Laboratory, USA; N. Bergmann, Queensland University of Technology, Australia An Application Approach to Evolvable Hardware |
| 12:20 - 12:40 | N. Macias, USA The PIG Paradigm: The Design and Use of a Massively Parallel Fine Grained Self-Reconfigurable Infinitely Scalable Architecture |
| 12:40 - 2:00 |
Lunch |
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Session 9: Advanced Reconfigurable Devices Chair: J. Moreno, Technical University of Catalunya, Spain |
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| 2:00 - 2:20 |
J. Moreno, J. Madrenas, J. Cabestany, E. Canto, Technical University of Catalunya, Spain; R. Kielbik, Technical University of Lodz, Poland; J. Faura, J.M. Insenser, SIDSA, PTM, Spain Realization of Self-Repairing and Evolvable Hardware Structures by Means of Implicit Self-Configuration |
| 2:20 - 2:40 |
J. McDonald, B. Goda, Rensselaer Polytechnic Institute, USA Reconfigurable FPGA's in the 1-20 GHz Band with HBT BiCMOS |
| 2:40 - 3:00 |
K. Asari, Y. Mitsuyama, T. Onoye, I. Shirakawa, H. Hirano, T. Honda, T. Otsuki, T. Baba, T. Meng, Matsushita Electronics Corp., Japan; Osaka University, Japan; Panasonic Technologies, USA; Stanford University, USA FeRAM Circuit Technology for System on a Chip |
| 3:00 - 3:10 |
Break |
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Session 10: GA Applications Chair: B. Toomarian, JPL, USA |
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| 3:10 - 3:30 |
T. Cwik, G. Klimek, Jet Propulsion Laboratory, Caltech, USA Genetically Engineered Microelectronic Infrared Filters |
| 3:30 - 3:50 |
G. Klimek, C. Salazar-Lazaro, A. Stoica, T. Cwik, Jet Propulsion Laboratory, Caltech, USA "Genetically Engineered" Nanoelectronics |
| 3:50 - 4:10 |
P. van Remortel, T. Lenaerts, B. Manderick, Brussels Free University, Belgium The Evolution of ROBDDs: Preliminary Results and a First Analysis |
| 4:10 - 4:30 |
J. Masner, J. Cavalieri, J. Frenzel, J. Foster, University of Idaho, USA Representation and Robustness for Evolved Sorting Networks |
| 4:30 - 4:50 |
P. Chongstitvatana, C. Aporntewan, Chulalongkorn University, Thailand Improving Correctness of Finite-State Machine Synthesis from Multiple Partial Input/Output Sequences |
| 4:50 - 5:00 | Conclusions |