| US 7,407,832 B2 | ||
| Method for manufacturing semiconductor package | ||
| Yasuki Ogawa, Miyazaki (Japan) | ||
| Assigned to Oki Electric Industry Co., Ltd., Tokyo (Japan) | ||
| Filed on Aug. 18, 2006, as Appl. No. 11/505,920. | ||
| Claims priority of application No. 2005-263516 (JP), filed on Sep. 12, 2005. | ||
| Prior Publication US 2007/0059860 A1, Mar. 15, 2007 | ||
| Int. Cl. H01L 21/44 (2006.01) | ||
| U.S. Cl. 438—106 [438/112; 438/124; 438/127; 257/E21.504; 257/E23.125; 156/500; 249/95; 425/116] | 12 Claims |
| 1. A method for manufacturing a semiconductor package, comprising:
preparing a die provided with at least one first half and at least one second half coupled together to form a cavity therebetween,
said first half having a satin-finished inner surface and an ejector-pin-through-hole extending therethrough,
inserting an ejector pin having a mirror-finished surface at a tip end thereof into said ejector-pin-through-hole, positioning
said ejector pin at a position where a surface of said tip end of said ejector pin coincides with an intermediate surface
height of said satin-finished inner surface of said first half, and fixing said ejector pin at said position, and
embedding an IC structural body having a lead, an IC chip, and bonding wires bonded between the lead and the IC chip within
a molten resin filled in said cavity, after said IC structural body is confined within said cavity.
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