US 7,468,754 B2 | ||
High-definition de-interlacing and frame doubling circuit and method | ||
Eric Stephen Carlsgaard, Zionsville, Ind. (US); David Leon Simpson, Fishers, Ind. (US); and Michael Evan Crabb, Hamilton County, Ind. (US) | ||
Assigned to Thomson Licensing, Boulogne-Billancourt (France) | ||
Filed on Jan. 14, 2005, as Appl. No. 11/36,920. | ||
Application 11/036920 is a continuation of application No. 10/190282, filed on Jul. 05, 2002, granted, now 6,894,726. | ||
Prior Publication US 2005/0162549 A1, Jul. 28, 2005 | ||
This patent is subject to a terminal disclaimer. | ||
Int. Cl. H04N 7/01 (2006.01); H04N 11/20 (2006.01) |
U.S. Cl. 348—448 [348/459; 348/911; 348/456; 348/455; 348/441] | 6 Claims |
4. A method for de-interlacing interlaced video, comprising the steps of:
reading from a unitary memory each of two frames of video information at a rate of twice a normal frame rate;
performing, at a unitary combined de-interlacing and frame doubling circuit, two de-interlacing operations in parallel with
each other and at the same time, each de-interlacing operation being performed on a successive pair of video lines separate
from the other de-interlacing operation.
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