HTR FPGA Design for Source calibration and debugging

 version 0.5

User's Notes
Tullio Grassi (Tullio@physics.umd.edu) - 29 Oct 2001

The HTR demo board with the FPGA design version 0.2, is designed for the source calibration and for debugging.
There are 3 operation modes:

  1. Source Calibration
  2. Repetitive (to inject data to DCC)
  3. Pure Data Stream (for testing with the FE-emulator)

Board modification required with this version!!

Make sure  R10 is removed.
R22 (= 50 Ohm termination) has to be removed if lemo_clock from FEemulator
Put a wire from pin 2 (the top one) of J22 to pin1 (the bottom one) of R22.
Jumper J22 disconnected.
Jumper J23 indifferent.
 

 Front-Panel

Objects on the front panel of the board, from top to bottom (all TTL signals, unless stated differently):
 
LEFT RIGHT
Lemo (test output)  
Lemo (clock INPUT) Lemo (clock OUTPUT)
Subset of parallel DAQ bus OUTPUT   
Channel Link OUTPUT (DAQ data)  
GLink optical Inputs 4&3 - Keep the caps on if not in use: dust sensitive!  
GLink optical Inputs 2&1 - Keep the caps on if not in use: dust sensitive!  
Push-Botton Reset (Global Reset and Channel Link LVDS power-down)  
LEDs[0-9]  
Rotary switch - 10 positions  
Lemo Trigger IN (not used) Lemo Self-Trigger OUT - ECL (not active) 
Lemo RX_CLK (not used) Lemo RX_BC0 (not used)

Clocking

The recovered clock is used as a board system clock.
The input lemo clock is necessary as a reference clock for the GLink rx.
The nominal range of frequency supported is 20 MHz - 45 MHz.

DAQ Data Output

The  DS90CR285 Channel Link driver has 28 inputs: TXIN[27..0] = L2FRAME[27..0].
They correspond to the 16 DAQ data D[15..0], the 2 status bits S[1..0], the 5 Hamming bits H[4..0] and the parity bit P,
as defined on the HTR-- DCC link format: http://ohm.bu.edu/~hazen/my_d0/TxRx/Hamming.pdf
18 of them are sent on the 20-pin connector, according to the following table:
 
Pin Signal   Pin Signal
20 (top left) TXIN2 = D0   19 TXIN4 = D1
18 TXIN5 = D2   17 TXIN6 = D3
16 TXIN8 = D4   15 TXIN9 = D5
14 TXIN10 = D6   13 TXIN11 = D7
12 TXIN15 = H4   11 TXIN17 = D12
10 TXIN18 = D13   9 TXIN19 = D14
8 TXIN21 = S0   7 TXIN22 = S1
6 TXIN23 = P   5 TXIN24 unused ('0')
4 TXIN26 unused ('0')   3 TXIN27 unused ('0')
2 GND   1 (bottom-down) GND

Rotary Switch

To make sure of you selection,  turn the switch counter-clockwise until it stops.
Now it is on position zero. Turn it one step at the time clockwise to increase the position.
 
Position Selection DAQ-Output
(and 20-pin conn.)		 Two PMC connectors
0 Source mode fiber 2  fibers 1&2
1 Repetitive mode internal counter  fibers 1&2
2 Data Stream mode  fiber 2  fibers 1&2
3 Data Stream mode  fiber 2  fibers 3&4
... not used    
...  ...    
       

LEDs

LED # (from top) Signal Notes
0 (Scaled_Sys_clk) OR (PB_Reset) During normal operation you should see a blinking light. The light stays on while you push the reset botton
1 G-Link4 OK (the top one) Light = (RX_ERR) AND (NOT RX_READY).        Light is on if not working.
2 G-Link3 OK Light = (RX_ERR) AND (NOT RX_READY).        Light is on if not working.
3 G-Link2 OK Light = (RX_ERR) AND (NOT RX_READY).        Light is on if not working.
4 G-Link1 OK (the bottom one) Light = (RX_ERR) AND (NOT RX_READY).        Light is on if not working.
5 unused  
6 Source mode Light on if the rotary switch is in position 0
7 Repetitive mode Light on if the rotary switch is in position 1
8 Data Stream mode (fibers 1&2) Light on if the rotary switch is in position 2
9 Data Stream mode (fibers 3&4) Light on if the rotary switch is in position 3

DAQ-output format

For all the 3 operating modes the output to DCC is formatted in blocks with the same structure. Each block has  FB(Hex)=251(Decimal) words.
Consecutive blocks are separated by one IDLE word [S1=0; S0 =0]
Block structure follows:
 
DAQ-word DAQ-word content D[15..0] [S1,S0]
HEADER [0...0 , block_no(7..0)] 11
DATA 0...0 (available) 10
DATA Block_no[15..0] 10
DATA Block_no[31..16] 10
DATA Data word 0 10
DATA Data word 1 10
... ... ...
DATA Data word  10
DATA Data word  10
DATA 0...0 (available) 10
TRAILER [block_no(7..0), 0...0] 01
IDLE don't care 00

NB: around a DAQ-block edge seven words are lost.
When Glink mode goes from DATA to something else, the block is interrupted with the Trailer word;
an extra zero DAQ-word can be generated to guarantee the even number of words.

1- Source Calibration mode

The purpose of this mode is to use the HTR for the source calibration test at Fermilab with the Front-End readout electronics.
Only one fiber is needed, as one fiber carries 2 QIE_channels, one for the source data and the second one as a reference.
The optical receiver will be the number 2: plug the fiber in the 2nd place from bottom (that is on the top slot of the bottom dual receiver).
During normal operations, the FE G-link transmitter sends only IDLE and DATA words.
The G-Link words are converted to DAQ-word as in the following table:
 
GLink word DAQ-word
IDLE IDLE
CONTROL IDLE
DATA HEADER, DATA, TRAILER

The 16-bit FEdata[15:0] input has the following fields:
 
FEdata(15:14)  FEdata(13:12)  FEdata(11:7)  FEdata(6:5)  FEdata(4:0)
CapID_B(1:0)  Exp_B(1:0)  Mant_B(4:0) Exp_A(1:0)  Mant_A(4:0)

The 16-bit DAQ-data output D(15:0) has the following fields:
 
D(15:14) D(13) D(12) D(11:7) D(6) D(5) D(4:0)
CapID_B(1:0)  CapID error G-Link error Mant_B(4:0) Exp_B(1) OR Exp_A(1) Exp_B(0) OR Exp_A(0) Mant_A(4:0)

The 16-bit output data D(15:0) are encapsulated in the DAQ-output format described above.

CapID_B(1:0) are supposed to change ciclicaly: ...,00, 01, 10, 11, 00, 01, ...
When this sequence is violated then the CapID error bit is asserted.
CapID error is in the same clock slot of the word tha violated the sequence.
NB:  when GLink goes from IDLE to DATA (or CONTROL) mode, the first word can generate a spourious CapID error

2- Repetitive mode

In this mode the HTR runs an internal 16-bit counter sending data to the DAQ-output with the usual block structure.
 

3- Pure Data Stream mode

Input data (from Fiber2) are sent to the DAQ-output with the usual block structure.
That is :  (RX[15..0] of fiber 2) = (D[15..0] of DAQ data).

Output on PMC connectors

Data from 2 fibers (with the corresponding RX_ERR, RX_CNTL, RX_DATA) are sent to the 2 PMC connectors on the bottom-left
area of the board, according to the following figures.

If Rotary switch = 0,1,2, then data from fibers 1&2 are sent out.
 


 
 

If Rotary switch = 3, then data from fibers 3&4 are sent out.


 
 
 

Other notes

Keep the caps on the optical receivers if not in use: they are dust sensitive!
At power-on the Apex device generates a 96 ms RESET_b pulse.
A watch-dog circuit monitor the TTCrx daughter card and sends periodic reset pulses if TTCRXREADY=0.
Power from the VME backplane:  +5V and optionally +3.3V.
A local switching regulator (U11) can generate 3.3V from 5V: set the nearby jumper (P3) according to the need (3.3V from VME or from REGulator).

G-Link receiver settings:

   SHFIN = 0
    PASSENB = 0
    RXFLGENB = 0
    ESMPXENB = 0  (when on-board red switch 3 is OFF = up )
    RXDIV1 = 0    (constant )
    RXDIV0 = 1    (constant )

On-board switch 1 inverts or let uninverted the clock sent to the Channel Link TX and to the GLink RX (CK_Apex).
On-board switch 2 disables the watch-dog circuitry for the TTCrx (i.e. inhibits the generation of TTCreset when TTC is
not ready).
On-board switch 3 control the Glink setting ESMPXENB.Default ESMPXENB = 0  (when switch is OFF = up ).

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Zipped files


Programming file for passive serial configuration as fixed in BU (htr_BU.sof).
Zipped design directory htr_BU.zip generated with Quartus II v1.0.
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