| US 7,383,370 B1 | ||
| Arbiter circuit and signal arbitration method | ||
| Sanjay Sancheti, Sunnyvale, Calif. (US); and Gareth Feighery, San Mateo, Calif. (US) | ||
| Assigned to Cypress Semiconductor Corporation, San Jose, Calif. (US) | ||
| Filed on Mar. 20, 2006, as Appl. No. 11/384,748. | ||
| Claims priority of provisional application 60/666983, filed on Mar. 31, 2005. | ||
| Int. Cl. G06F 13/00 (2006.01) | ||
| U.S. Cl. 710—241 [326/94; 327/19] | 20 Claims |
| 1. An arbiter circuit, comprising,
a latch circuit that is coupled to receive a first input signal and a second inputs signal, each input signal having a match
state and a no match state, the latch circuit being driven to a forced state in response to an active kick signal;
a filter section coupled to the latch circuit, the filter section driving arbiter output values to a first set of values when
the latch circuit is in a metastable state in response to the first and second input signals having the match state, and driving
the arbiter output values to a second set of values in response to the first and second input signals having the no match
state; and
a kick signal generator, coupled to receive at least the first and second input signals, which activates' the kick signal
after a predetermined delay in response to the first and second input signals having the match state.
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