INTRODUCTION

MODULE DESCRIPTION & INTERFACES

Figure 1. Data Collection Interface Module Block Diagram

Each MCM serial stream consists of two data lines (SDATA1,2) coupled with a common clock line (SCLK). The system is functionally partitioned so that 2 MCM serial data channels are handled by a pair of Xilinx XC4010E FPGAs, allowing partitioning of the serial translator and data formatting functions. Table 1 details the contents of the serial string from the MCMs. Each 10-bit word sent contains a parity bit in the most significant bit.

The start bit is defined as four rising edges of the SDATA1 line while SCLK is asserted high. The stop bit is four rising edges of the SDATA2 data line while the SCLK line is asserted high. When SCLK goes low, the requirement on the start and stop bit is reset, and the circuit begins again looking for consecutive edges on the data lines. When a start bit is detected, the data is clocked out and synchronized so that the rising edge of the SCLK is in the middle of each data bit. The first data word appears on SDATA1, and the second word is clocked out on SDATA2, beginning with the sixth bit of the first word on SDATA1. Thus, the serial data is staggered but is always synchronized with SCLK.

Serial data from the MCM is translated from LVDS to TTL levels, and is formed into parallel words by the Serial Translator FPGA, which checks parity for bit errors and logs framing errors before writing the data to a FIFO. From the data contained in the FIFOs, the Formatting and Output Control FPGA adds the module address (set by jumper on the DCIM PCB), header and trailer words, and 8 user words. Formatted event data packets, consisting of 20-bit words, are transmitted to the DCMs via GLink at ~19 Mb/sec (2X Beam Clock rate). The output data packet format for each of the GLink channels is outlined in Table 2.

The DCIM is designed to handle serial data errors in limited fashion. Two error conditions are dealt with at the DCIM level -- framing and data errors. Framing errors include incorrect packet formatting, length, or start/end bit sequencing errors and are easily detectable. If a packet error occurs, a reserved bit in the 18-bit FIFO data is set and maintained for the first occurrence and every word thereafter for the duration of the packet. The errors and set bits are as follows:

At initial installation of the PHENIX detector, the MCM to DCM ratio will be 2, changing to 1 as the remaining group of DCMs are purchased and installed at a future date. Operation in either mode (ratios of 2:1 and 1:1) is accomplished using the reprogrammability of the FPGAs and two channel enable bits ENDAT[0,1]. These bits indicate which of the 2 multiplexed channels (odd or even) transmit data over the shared GLink channel. The data formatting and control FPGA handles this function. Each channel is hard-wired on the PCB as either even or odd.

INTERFACES

Three separate backplane connectors were selected for use in each crate -- one providing both power and signal distribution, and two additional connectors for supplying power. The estimated power requirements detailed in later sections provide the justification for this additional connector. The signals were grouped according to function, speed, and noise susceptibility, and assigned to the three connectors as shown in Tables 3, 4, and 5, which are found at the end of this document. Power was split into 4 separate supplies: +5V_D (digital power), +5V_GL (GLink power), and (12V_A (analog power). Grounds associated with each supply are also split accordingly to allow flexibility for crate grounding optimization. Additionally, extra signals (identified by * suffix) are assigned to each group and will be incorporated into module buffering for future expansion if necessary. Figure 2 shows the DCIM's I/O connectors and their general location on the PCB. Front panel mounted LED's were added to the design to allow external observation of the board power and FGPA DONE conditions.

Programming of the FPGAs is accomplished via the ARCNet-controlled VME backplane bus or a header on the board which is provided for testing purposes. The FPGAs are programmed as 3 groups of 2 serially connected units. Upon being programmed the DCIM has built-in capability for allowing polling of the 'DONE' bit of each FPGA individually using the backplane signals provided. This ensures proper system functionality. The FPGA's are clocked by a 4X Beam Clock signal which is produced on the board using a frequency synthesizer with the Beam Clock as its input. The frequency synthesizer is the exact design used in the Timing & Control Interface Module and other test fixtures associated with MVD.

PCB DESIGN & LAYOUT CONSIDERATIONS

Figure 2. DCIM Physical Layout and Connector Location