Workshop on Functionality of Hardware Performance Monitors (FHPM) Micro 39
Saturday December 9th
Schedule:
|
08:00 – 08:30 |
Poster setup |
|---|---|
|
08:30 – 08:45 |
Welcome and Introduction |
|
08:45 – 09:15 |
Jim Callister (Intel) “HPM Futures and Visions” |
|
09:15 – 10:00 |
Jeffery Keil (Nvidia) “GPU Performance Analysis: A Developer's Perspective” |
|
10:00 - 10:30 |
Break and Posters |
|
10:30 – 11:15 |
Wilson Snyder and Phil Mucci (SiCortex) “Designing a HPM from Scratch- A Thousand Events, Please.” |
|
11:15 – 12:00 |
Reza Azimi (University of Toronto) “Enhancing Operating System Algorithms through Hardware Performance Monitoring”
Matthew Curtis-Maury (Virginia Tech) “Dynamic Program Stirring on Multiple Cores: How Hardware Performance Monitors Can Help Regulate Performance, Power, and Temperature Simultaneously” |
|
12:00 - 01:30 |
Lunch |
|
01:30 - 03:00 |
Alex Mericas (IBM) “Power Update, Cell HPM and What’s Hard About Multi-threading” |
|
03:00 - 03:30 |
Break and Posters |
|
03:30 – 04:15 |
Michael Kagan (Mellanox) “Infiniband HPM, Futures and Visions” |
|
04:15 – 04:45 |
Peggy Ireland (Intel) “Design of Xeon/Core 2/Duo HPM, Futures and Visions” |
|
04:45 – 05:30 |
Dave Christie and Anoop Iyer (AMD) “Performance Monitoring Features in AMD Barcelona ” |
|
05:30 – 06:00 |
Stephane Eranian (HP) “Challenges to a Standard Monitoring Interface”
Adam Leko (University of Florida) “Tool Infrastructure for Hardware Performance Counters” |
Abstracts:
Jim Calister (Intel) “HPM Futures and Vision”
Jeffrey Kiel (Nvidia) “GPU Performance Analysis: A Developer's Perspective”
As
GPU designs have become more complex, determining
pipeline
bottlenecks
and performance leaks has become even more difficult.
Since
internal
units interrelate more and more, directed tests to determine
performance utilization fail to capture the true performance profile
of the GPU. This talk will cover GPU performance issues from a
application developer's point of view:
*
GPU architectures and inherent performance issues
*
Types of performance monitoring signals available to developers
*
Tools available for performance tuning (APIs and interactive
applications)
Phil Mucci and Wilson Snider (SiCortex) - “Designing a HPM from Scratch- A Thousand Events, Please”
SiCortex discusses their performance counting architecture on a dense cluster CPU chip. They give a overview of the system, the microprocessor they designed, the performance measurement system, supporting software, and some lessons learned. Unique features include a scheme to sample between nearly a thousand performance events, which give their programmers an overview of performance while staying within their tight power and area budget.
Reza Azimi, David Tam, Livio Soares, and Michael Stumm (University of Toronto)
abstract link http://www.c3.lanl.gov/~mlang/azimi.pdf
Matthew Curtis-Maury, Dimitrios S. Nikolopoulos (Virgina Tech), and Christos Antonopoulos (William and Mary) - “Dynamic Program Stirring on Multiple Cores: How Hardware Performance Monitors Can Help Regulate Performance, Power, and Temperature Simultaneously”
abstract link http://www.c3.lanl.gov/~mlang/curtis.pdf
Alex Mericas (IBM) “Power Update, Cell HPM and What’s Hard About Multi-threading”
Michael Kagan (Mellanox) “Infiniband HPM, Futures and Visions”
Peggy Ireland (Intel) “Design of Xeon/Core 2/Duo HPM, Futures and Visions”
Dave Christie and Anoop Iyer (AMD) “Performance Monitoring Features in AMD Barcelona”
Stephane Eranian (HP) “Challenges to a Standard Monitoring Interface”
abstract link http://www.c3.lanl.gov/~mlang/eranian.pdf
Adam Leko (University of Florida) “Tool Infrastructure for Hardware Performance Counters”
abstract link http://www.c3.lanl.gov/~mlang/leko.pdf