| US 7,376,818 B2 | ||
| Program translator and processor | ||
| Kenichi Kawaguchi, Hyogo (Japan) | ||
| Assigned to Matsushita Electric Industrial Co., Ltd., Osaka (Japan) | ||
| Filed on Jul. 18, 2003, as Appl. No. 10/621,440. | ||
| Application 10/621440 is a division of application No. 09/536308, filed on Mar. 27, 2000, granted, now 6,658,560. | ||
| Claims priority of application No. 11-086561 (JP), filed on Mar. 29, 1999. | ||
| Prior Publication US 2004/0019766 A1, Jan. 29, 2004 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G06F 9/38 (2006.01); G06F 9/52 (2006.01) | ||
| U.S. Cl. 712—226 [712/208; 712/245] | 2 Claims |
| 1. A processor comprising:
an instruction register which stores two instructions;
a decoder which decodes the two instructions;
a first execution unit;
a second execution unit; and
instruction parallelizing/executing means, coupled to said decoder, for executing the two instructions, which designate the
first execution unit as a target, in parallel by allocating one of the two instructions to the second execution unit,
wherein the parallelizing/executing means converts one of the two instructions to another equivalent instruction that designates
the second execution unit as a target.
|