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[SVX II Chip] [Silicon Readout] [Fiber Tracker Readout]
The readout for both the silicon vertex detector and the fiber tracker is based on the 128 channel SVX II chip developed by Fermilab and LBL. Each channel contains a double-correlated sampling charge sensitive preamp, 32 stages of analog pipeline delay, a Wilkinson 8 bit analog to digital converter and a sparse data readout system ($<5\mu$s for ~3% occupancy). The readout system employs a common digital threshold for all 128 channels. It also implements a `nearest neighbor' readout scheme in which two channels below threshold neighboring a channel above threshold will also be read out. The chip is designed to accept data every 132 ns. At this crossing frequency, the 32 channel delay stage provides 4.2$\mu$s for the Level 1 trigger decision. For the silicon tracking system, this chip is mounted directly on the detector. Two iterations of the SVX II chip have been prototyped in standard CMOS and tested. All parts of the chip are fully functional and the noise has been measured to be $\sigma = 450 e + 65 e$/pF for a risetime of 105 ns.
Figure 5 is a block diagram of the silicon readout system. The SVX II's are controlled by a readout card, called a port card, which is mounted in the detector platform. The silicon detector is connected to the port card by a 28 foot long metallic data path. The port card downloads the parameters to the SVX II chips, controls the chip during data taking, reads out the data after a Level 1 trigger and converts the data to optical signals and sends these signals over fiber optic cables to the moving counting house. It also provides temperature, voltage and current monitoring and some level of diagnostics. It generates the test pulse signal for the SVX II.
The optical signals are received in the Moving Counting House by the Silicon Acquisition and Readout board (SAR), a VME board that acts as a buffer for transferring data to the Level 3 system. Events are held in one of eight local buffers until a valid Level 2 accept is received, when they are sent to the existing VME buffer driver (VBD) for transmission to the Level 3 system. Level 2 rejects are discarded.
The front-end electronics for the fiber tracker must provide a prompt Level 1 trigger pickoff, necessitating the development of a special `precursor' chip between the VLPC and the SVX II. Each channel of this chip has a charge sensitive amplifier, a discriminator with TTL output and a buffer amplifier to put charge onto an output capacitor which is read by the SVX II chip. In order to prevent the chip from oscillating, the trigger is picked off with a different clock cycle than both the input and the transfer to the SVX II. The readout after the SVX II is nearly identical to that for the silicon system.
The trigger scheme for the fiber tracker is based upon the r-$phi$ hit patterns in 4.5 degree sectors and allows four distinct momentum thresholds. The output from the trigger pickoff chip is fed into a series of large Field Programmable Gate Arrays which are preloaded with the appropriate logic to form hits from the eight trigger layers. The FPGA's are static RAM, so thresholds are software settable. Trigger data is combined with the preshower detector on the trigger board and sent serially at 424 Mhz to other trigger systems.