SVX4 Testing Meeting Minutes 2/12/03
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Brad gave an update on the simulation status. He ran a series of 
full chip (nanosim) simulations. The resulting tarred data base files 
are available.  Brad recommends looking at these files with simwave. 
Predefined configuration files (.sv files) are available which should 
allow an easy start. (Tom said that Jim Hoff has simwave running at FNAL)


In the simulations the chip data is read out properly but there is a 
funny shift of pedestal for some cells. E.g. for the chip version A, 
all channels starting from channel number 55 show a pedestal increase 
of 11 ADC. (See Brad's recent e-mail for more details.)

Since this is a schematic level simulation (no parasitics) all channels 
should be treated equally and the effect is believed to be a simulator 
artifact. A small discussion evolved what could be done to understand 
this further and some proposals were made. For now Brad will focus on 
getting the chips ready for submission, while working on the above 
problem in the background. 

Brad expects to provide gds files by February 18. DRC Antenna runs were 
done. Currently LVS size mismatches are being fixed and LVS is run on 
version B.


William commented on the PO status. MOUs are completely signed off. The 
order will start going through procurement now and the bureaucracy should 
be finished within a week or so. 

One more wafer has been tested by William et al. Only one power short was 
found. All chips were tested using the Svxscope package and displayed 
the proper pedestal levels and correct data structure.


Physicists of the BNL Phenix heavy ion experiment have been visiting FNAL. 
They are interested in using SVX4 chips. They would need of the order of 
4000 (four thousand) chips. 

Marc