MODULE SERIN
@ALTERNATE;
"History:
" 17-Sep-96 DH Checksum=8A8C

CLK	pin	1		;" 16 MHz Clock
SIN	pin	2		;" Serial input
DONE	pin	3		;" Done from FPGA

START	pin	14='pos,reg'	;" Detected rising edge on SIN
CDAT	pin	15='pos,reg'	;" Synced SIN
CNT0	pin	16='pos,reg'	;" 4-bit cell counter 16 clocks/cell
CNT1	pin	17='pos,reg'	;" 4-bit cell counter 16 clocks/cell
CNT2	pin	18='pos,reg'	;" 4-bit cell counter 16 clocks/cell
CNT3	pin	19='pos,reg'	;" 4-bit cell counter 16 clocks/cell
/CCLK	pin	20='pos,reg'	;" CCLK to FPGA
/PRGRM	pin	21='pos,reg'	;" Program/reset pulse to FPGA
RCTIME	pin	22		;" R/C time constant of 1ms

equations

"High on SIN for 1ms is a reset signal
RCTIME    = 1;		;" Drive high or not at all
RCTIME.OE = /SIN;	;" Let Resistor pull low if SIN high
PRGRM := /RCTIME.pin;	;" RC is low, assert PRGRM(RESET)

" A bit for programming the FPGA consist of three bit cells
" that are each 1 uS (16 clocks).  The first bit cell is
" a high start bit.  The second is the data bit.  The third
" is a low stop bit.
" This circuit detects the start bit and then waits 1.5 uS to
" sample the data bit (CDAT) on the rising edge of /CCLK.
"         ________________________________________________
"SIN    _//                       \\_____________________
"           ________________________________________
"START    _/                                        \_____________
"               ______________________________________________
"CDAT     _____/      START BIT       \________DATA_BIT________
"
"CNT       [ 0 | 1 | 2 | ... 14 | 15 | .... 23 | 24 | 25 | ... 
"         ___________________________                ___________
"/CCLK                               \______________/
"

START := /DONE*SIN*/CDAT	 " Start on rising edge of SIN
      + START*/(CCLK*CNT3)	;" Hold for 25 clocks

CDAT  := (START+CDAT)*SIN	;" Follow SIN synced to START.

CNT0  := START * /CNT0 ;
CNT1  := START * (CNT1 :+: CNT0) ;
CNT2  := START * (CNT2 :+: (CNT1*CNT0)) ;
CNT3  := START * (CNT3 :+: (CNT2*CNT1*CNT0)) ;

CCLK  := START * CNT3*CNT2*CNT1*CNT0
       + START * CCLK* /CNT3 ;	;" Assert CCLK at 16 clocks for 8 clocks.

END