E907 MIPP TPC
Trigger and Cables

Sections

Triggers and Gates
Busies
Signals at RR06 Patch Panel
Anode High Voltage Cables and Channels

Triggers and Gates

Schematic

MIPP TPC Trigger schematic

Timing Diagram

MIPP TPC Trigger timing diagram

Notes

EXP TRG
EXPeriment TRiGger [NIM]
The global experiment trigger. The timing diagram gives delays with respect to the edge of EXP TRG at RR06. This is probably ~100 ns after the signal is first formed downstream of JGG in the main trigger crates.
TPC CLK/TRG
TPC CLocK and TRiGger module [mixed]
This module has two functions. First, it houses the free-running TPC CLK, which runs at 20 MHz. Second, it synchronizes the TPC GATE with the next TPC CLK edge, generating TPC TRG, to give the TPC front end sticks a synchronous trigger. TPC TRG ends with TPC GATE.

If the TPC GATE is shorter than the time required for the number of time buckets configured through slow control, the sticks stop converting and the data stream on the fibers is interrupted abruptly. The current receiver card software is unable to handle this condition, since it is expecting a well-formed data stream. In principle, this feature could be used to implement a fast-clear.

This module puts the TPC CLK and TPC TRG, as ECL differential pairs, on a 10-pin ribbon cable. Both signals are also available at the front panel as NIM levels.

TPC TRG goes back to RR06 and into the TPC TDC.
TPC CLK/TRG FANOUT
TPC CLocK and TRiGger FANOUT [ECL]
This module replicates the TPC CLK and TPC TRG signals for distribution to the front end sticks.
TPC GATE DELAY
TPC conversion GATE DELAY [NIM]
The Gating Grid driver takes a significant amount of time to become transparent. During the transition, it induces noise on all the pads, which which forces the receiver cards to scan every time bucket for real hits, leading to the worst case 16 ms dead time. The TPC GATE DELAY delays the start of digitization until after this transient.
TPC GATE
TPC conversion GATE [NIM/TTL]
The window during which the TPC front end sticks should digitize. The NIM signal is converted to TTL in RR06 before being sent to the CLK/TRG module in RR08.
GG GATE
Gating Grid GATE [NIM/TTL]
The duration the gating grid should be transparent. The NIM signal from the 2323A gate generator is converted to TTL for the Gating Grid Drivers. The single gate is T'ed in RR07 to feed the INPUT and ENABLE inputs on both drivers.
TPC TDC
TPC Time-to-Digital Converter
The two LRS 4208 modules serve two functions. First, one module digitizes TPC TRG. This signal has 50 ns of jitter, event to event, because it synched to the asynchronous (w.r.t. the EXP TRG TPC 20 MHz clock.

Second, they each have six channels configured as two multi-hit channels, which look at the Gating Grid monitor pulses.

The TPC TDC's are started by EXP TRG, and stopped by the individual channel inputs, limted by the TPC TDC EDW gate.
TPC TDC EDW
TPC TDC End Data Window
Because of their very wide range, the TPC TDC's can introduce dead time if allowed to run to the end of the range. The TPC TDC EDW gate limits the conversion range to a more reasonable value.
TPC BUSY
All gates, all DSP busses, and all TPC VME PowerPC processor busies are OR'ed to form a single TPC BUSY. This signal is fed back to the main experiment busy.

Busies

TPC VME Crate Busies:
    The VME crates supply two busies, each, one from the PPC, one  from the set of DSPs.
    These arrive on the patch panel, go in a bundle

    to RR06 NC04? Slot 12 PS726, then NIM outputs to TPC BUSY
Busy Input Patch Panel PS726 Ch
TPC DSP A C10 8
TPC DSP B D10 9
TPC DSP C D9 10
TPC DSP D C9 11
TPC PPC A C12 12
TPC PPC B D12 13
TPC PPC C D11 14
TPC PPC D C11 15 
GG GATE BUSYbar
    (RR06 CC 08? Slot 20 LeCroy 2323A Ch B):
    NIMbar output

    to RR06 NC05? Slot 12 LeCroy 429A FIFO 4x4 Ch 0
    NIMbar output GG GATE BUSY to TPC BUSY


TPC DELAY BUSY 
    (RR06 CC 08? Slot 22 LeCroy 2323A Ch A):
    NIM output to TPC BUSY


TPC GATE BUSYbar 
    (RR06 CC 08? Slot 22 LeCroy 2323A Ch B):
    NIMbar output

    to RR06 NC05? Slot 12 LeCroy 429A FIFO 4x4 Ch 1
    NIMbar output TPC GATE BUSY to TPC BUSY


TPC BUSY 
    (RR06 NC05? Slot 11 LeCroy 429A FIFO 1x16):
    NIM output

    to RR06 NC05? Slot 8 LeCroy 429A FIFO 2x8 Ch 1

    Earliest busy edge generated at t = 60 ns.

TPC Signals at RR06 Patch Panel

Signal Value Patch Panel Cable Label Notes
TPC GATE TTL A8 SB7 conversion gate, >16 ms for 256 buckets
TPC TRG TTL B8 SB8 to TDC
GG GATE TTL C8 LG2 gate input to both GG drivers, 20 mus
TPC CLK TTL D8 SB12 TPC free running 10 MHz clock monitor
GG0 VGGH 100:1 A14 LG6 output pulse monitor
GG0 VGGL 100:1 B14 LG7 output pulse monitor
GG1 VGGH 100:1 C14 LG11 output pulse monitor
GG1 VGGL 100:1 D14 LG12 output pulse monitor
GG0 POS 100:1 A15 LG3 DC monitor
GG0 NEG 100:1 B15 LG4 DC monitor
GG0 OFF 100:1 C15 LG5 DC monitor
GG1 POS 100:1 A16 LG8 DC monitor
GG1 NEG 100:1 B16 LG9 DC monitor
GG1 OFF 100:1 C16 LG10 DC monitor
spare   D15 SB14 TPC RR08 local pulser
spare   D16 LG1 spare

Anode High Voltage Cables and Channels

Anode Cable Label 1440 Crate
Slot Channel
0 BA-V-083 14 0
1 BA-V-088 12 1
2 BA-V-086 12 2
3 BA-V-085 12 3
4 BA-V-093 12 4
5 BA-V-096 12 5
6 BA-V-092 14 6
7 BA-V-095 12 7
8 BA-V-094 13 0
9 BA-V-091 13 1
10 BA-V-090 13 2
11 2 13 3
12 6 13 4
13 3 13 5
14 1 13 6
15 4 13 7

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