Reliability Issues

Reliability can be impacted by the same type of problems that are encountered in conventional parts packaging.  Figure 4 provides a fishbone diagram of typical failure modes of traditionally packaged integrated circuits.  For embedded die technology the entire top half of the chart can be eliminated if the process starts with a Known Good Die.   Moisture and contamination are the greatest concerns.  Both moisture ingress and contamination are minimized by the three barriers mentioned above – coating, gel, and lid.  Preliminary testing indicates that this approach appears successful; however, long-term reliability testing is required.  A side benefit to the cavity coating is that wire bond strength is increased by a factor of approximately 7 over uncoated wire bonds.  The introduction of contamination during fabrication is a potential problem. This obstacle   can be overcome by rigorous process controls and a disciplined assembly approach. 

Vias are another potential failure mode.  This is driven largely by the aspect ratio of the vias and the mechanical properties of the copper plating.  To lessen the risk of via problems, aspect ratios should be held as low as possible.

Future of Technology

Embedded circuitry is attractive for electronics that must be reliable in harsh environments over long duty cycles and where passive cooling is required.  Embedded circuitry is also attractive where large shock loads are expected.  NASA/MSFC first became interested in embedded circuitry because of the possibility of extending the mean time between failures of assemblies by eliminating a large percentage of the total interconnections as well as eliminating or significantly minimizing solder as a method of interconnect.  Also, embedded circuitry can operate at lower temperatures than traditionally packaged assemblies due to mounting of heat producing elements directly on a thermally conductive core. 

Currently, MSFC has two EPT tasks funded:  (1) Reliability Testing of Single Substrate EPT Assemblies, and (2) Development of Vertical Interconnects to Enable Module/Box-level Packaging Using EPT. 

The reliability testing of EPT subassemblies (shown in Figure 3) is a MSFC Center Director’s Discretionary Fund project for FY04-05.  Eight assemblies have been designed and fabricated.  The assemblies include two daisy chained die per assembly and six passive components.  The core thicknesses range between 0.010” to 0.040”.  Two different die attach materials are used in the test vehicles - traditional epoxy-based die attach and silicone-based die attach.  The test vehicles will be exposed to random vibration and long term thermal testing (-55°C to 125°C) and will be monitored for continuity throughout the testing.  Thermal testing will begin in December 2004 and is planned for 6000 cycles or until failure of 50% of the channels.  Destructive physical analysis will follow the testing.

Development ofvertical interconnects is an FY04 task funded by the Next Generation Launch Technology program.  This task started in April 2004.  MSFC designed three different test vehicles to assess the reliability of fuzz buttons as vertical interconnects between substrates.  The fuzz buttons are less than 0.8 mm in diameter and are fabricated from gold plated molybdenum wire.  MSFC will perform vibration and long term thermal testing.  Each test vehicle design uses a different configuration of fuzz buttons to determine the optimum design for the next phase of the EPT development.  See Figure 5 for an example of one of the vertical interconnect subassemblies.  Currently, this task is in the assembly phase with testing set to begin in January 2005.  Another method of vertical interconnects under consideration utilizes vacuum arc vapor deposited metal which is deposited in castellations, and possibly whole vias, to form interconnects between the substrates.  This method is not as attractive, however it is still under consideration and test vehicles may be fabricated to assess it in FY05. 

MSFC and JSC are studying the viability of packaging a global positioning system circuit in an EPT module to allow its use on various platforms.  Currently, the circuit is still in design and plans are to package the circuit using conventional methods and in parallel fabricate it using EPT.

MSFC is proposing to develop, fabricate and test a module-level design with daisy-chained die, stacked die, stress sensor die, passive components, stacked substrates and coefficient of thermal expansion matched composite cores as part of the NASA Independent Research and Development (IR&D) proposal call in 2005.  Figure 6 is the MSFC model of an embedded component that will be developed for the IR&D proposal.  If approved this project would begin in FY05 and would be a 24 month effort.

Ultimately, the goal of these efforts is to package an avionics component using EPT which would be an electronic cube with no air gaps, no solder joints and no structural housing (black-box). 

Potential Show Stoppers

Implementation of this technology is envisioned where size, modularity, passive cooling and/or reliability are drivers.  Application of this technology to power electronics is questionable and to facilitate its use may require traditional piggyback modules to house larger inductive elements.  Obviously, the up-front costs will be a deterrent in applications that do not have a specific need that EPT meets.   Also, where bare die aren’t available the efficacy of die harvesting is somewhat questionable as are the costs associated with it.  Repairability is also a concern that must be dealt with by risk mitigation strategies such as simulation and subassembly test.  A concern has been reported in literature [13] with silicone gel increasing stresses on wire bonds.  The current program at MSFC will investigate whether the increase in bond strength that results from coating application minimizes this concern.     Overall, there are no major show stoppers for most applications since this technology is based on building blocks of proven technology.

Technology Evolution

Near Term:

The near term evolution of this technology will be to implement it in module and box-level packaging for a standard space environment.  This will include both periphery and arrayed die, standard passive parts, and printed passive parts.  This architecture will need to be proven first in subscale extended environmental testing followed by qualification of functional modules/boxes.  Near term evolution should also consider use of this technology in extreme thermal and radiation environments.  Thermo-electric devices or similar should be incorporated to allow box-level control of the natural thermal environment.  For extreme cold environments (-120C and below) it may be necessary to incorporate either printed heaters or laminated foil heaters at various locations.   Initial box-level packaging should be optimized by radiation and thermal analysis techniques.  Densification of substrates is predicted to continue.  Currently, conductor width and spacing is around 5 mils.  In the near term, this can be driven to 4 mils.  Chip stacking is possible today and should be incorporated once the technology has passed some of the early tests.  Use of a composite core material with a coefficient of thermal expansion matched to silicon should be pursued and one candidate material is under investigation.  Development of reliable solderless interconnects for full array flip chips should be pursued in the near term.  Also, development of embedded power circuitry should be studied and if necessary a coupling of EPT and module technology should be employed to allow use of larger inductive devices.  Near term, design of assemblies for space use in non-critical applications could begin as early as FY2006.

Long-term:

Long term, the technology should be driven to the highest density level possible using standard printed wiring board manufacturing capabilities.  It is anticipated that conductor width and spacing can be driven to 2 mils or less and should be proven through subscale testing at this density.  Functionally the packages should be designed to stand alone by incorporating in-package power generation and wireless communications functions.  To accomplish this economically, advancement in ultra-low power technologies is necessary.  This would greatly increase modularity.   

Conclusions

EPT is a viable packaging technology that has many advantages over existing box-level architectures (see Table 2).  EPT as described herein is a viable technology for applications where smaller size/weight, robustness, reliability and/or passive cooling are drivers.  Although the TRL is estimated to be ~3 this could be rapidly increased to 6 or higher because the technology is built upon other proven technologies.

Enhancements to the technology, such as die stacking, substrate densification, and incorporation of CTE matched cores should be considered in future work.  Enhancements for application of the technology in extreme environments should be pursued in subscale test vehicles.

FY05 investments are recommended to support module-level design, fabrication, and test of EPT and development of solderless interconnect methods for full array flip-chips in laminates.