US 7,450,050 B2
Switched-capacitor reset architecture for opamp
Afshin Rezayee, Richmond Hill (Canada); Ken Martin, Toronto (Canada); and Aaron Buchwald, Newport Coast, Calif. (US)
Assigned to Snowbush, Inc., Toronto, Ontario (Canada)
Filed on Apr. 05, 2007, as Appl. No. 11/732,901.
Claims priority of provisional application 60/744314, filed on Apr. 05, 2006.
Prior Publication US 2007/0247348 A1, Oct. 25, 2007
Int. Cl. H03M 1/38 (2006.01)
U.S. Cl. 341—161  [341/155] 20 Claims
OG exemplary drawing
 
1. A pipelined analog to digital converter (ADC) comprising a plurality of pipelined stages, each stage comprising an analog to digital converter comprising a pair of comparators outputting signals to a multiplying digital to analog converter (MDAC), and the MDAC comprising an opamp and a reset circuit for the opamp, wherein the reset circuit including first and second capacitor elements and switching circuitry for precharging each of the first and second capacitor elements to the difference between input and output common-mode voltages of the opamp, and wherein during a reset phase of the MDAC, connecting the first capacitor between a positive input and a negative output of the opamp and connecting the second capacitor between a negative input and a positive output of the opamp to reset the opamp.