a forward portion having a reference input for receiving a reference clock signal and a feedback input for receiving a feedback signal; said forward portion having a forward portion output; said forward portion operable to generate an oscillating signal based on a phase or a frequency or a phase and frequency difference between said reference and feedback inputs; said oscillating signal being delivered from said forward portion output;

a delta-sigma modulator (DSM) having a DSM clock input for receiving a first driving clock signal; said DSM having a DSM input for receiving a high resolution input signal; said first driving clock signal having a frequency greater than said reference clock signal; said DSM having a DSM output; said DSM operable to generate a quantized bit-stream signal from said high resolution input signal that is delivered from said DSM output;

a fractional divider having a fractional divider input connected to said forward portion output for receiving said oscillating signal; said fractional divider having a control input connected to said DSM output for receiving said bit-stream signal; said fractional divider having a fractional divider driving clock input for receiving a second driving clock signal; said fractional divider having a fractional divider output for delivering a fractionally divided signal; said fractional divider operable, according to said bit-stream signal, to generate said fractionally divided signal having a frequency that is a fraction of said oscillating signal's frequency; and,

a feedback integer divider (FID) having a first FID input for receiving a representation of an integer value; said FID having a second FID input connected to said fractional divider output for receiving said fractionally divided signal; said FID having an FID output connected to said feedback input; said FID operable to frequency divide said fractionally divided signal by said integer value in order to generate said feedback signal.