| US 7,358,783 B1 | ||
| Voltage, temperature, and process independent programmable phase shift for PLL | ||
| Bonnie I. Wang, Cupertino, Calif. (US); Joseph Huang, San Jose, Calif. (US); Chiakang Sung, Milpitas, Calif. (US); Xiaobao Wang, Santa Clara, Calif. (US); In Whan Kim, Santa Clara, Calif. (US); Wayne Yeung, San Francisco, Calif. (US); and Khai Nguyen, San Jose, Calif. (US) | ||
| Assigned to Altera Corporation, San Jose, Calif. (US) | ||
| Filed on Mar. 25, 2003, as Appl. No. 10/400,191. | ||
| Application 10/400191 is a continuation of application No. 09/731473, filed on Dec. 05, 2000, granted, now 6,642,758. | ||
| Application 09/731473 is a continuation in part of application No. 09/432142, filed on Nov. 02, 1999, granted, now 6,369,624. | ||
| Claims priority of provisional application 60/169161, filed on Dec. 06, 1999. | ||
| Claims priority of provisional application 60/107166, filed on Nov. 05, 1998. | ||
| Claims priority of provisional application 60/107101, filed on Nov. 04, 1998. | ||
| Claims priority of provisional application 60/106876, filed on Nov. 03, 1998. | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H03L 7/095 (2006.01) | ||
| U.S. Cl. 327—156 [327/159; 327/160] | 19 Claims |
| 1. A phase-locked loop circuit comprising:
a voltage controlled oscillator providing a VCO clock output;
a first counter having a first clock input coupled to the VCO clock output; and
a second counter having a second clock input coupled to the VCO clock output, wherein:
the second counter generates an output clock of the phase-locked loop circuit;
a phase difference between the output clock and an input clock is programmably selectable by storing a first initial value
in a first memory of the second counter; and
a divider ratio of the second counter is stored in a second memory of the second counter.
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