Re: contribution on CERN pixels, silicon upgrades meeting 16 Jan 03

["Johann M. Heuser" <Johann.Heuser@cern.ch>]

Dear colleagues,

I should add one detail on the ALICE digital pilot chip that is relevant
to know for the discussion ALICE1LHCb-LHCBPIX1. As for the ALICE
specifications, the pilot chip clocks the pixel readout chips with 10 MHz,
even if those chips could be operated at higher speed. From that point of
view, the use of faster pixel readout chips alone would not be enough. Only
together with a different pilot chip or readout scheme.
For LHCb, the pilot chip is specific to meet the LHCb Level-0 requirements.

Best regards,
Johann


See Alex Kluge's web page:
http://a.home.cern.ch/a/akluge/www/work/alice/spd/spd_frame.html
--> The ALICE pixel pilot chip, version 1    Users manual

" The ALICE Pixel Pilot chip controls the readout of 10 pixel chips in a half
stave. It provides an interface to the Glink serializer (GOL). Also it receives
the trigger and configuration signals (trigger, test pulse and JTAG),
distributes the signals to the pixel chips, the analog pilot chip and the GOL.
...
The system is synchronously working. A 40 MHz clock is connected to the pilot
chip. The 40 MHz clock is passed on to the Glink serializer GOL. Otherwise the
clock is divided by 4
                    ** to generate the 10 MHz system clock.**
The pilot logic and the pixel chip logic work with the 10 MHz clock. As a
result all signals within the on detector pilot system OPS with the exception
of the GOL signals have a time binning of 100 ns. "


--
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| JOHANN M. HEUSER                 PHENIX Experiment at BNL, New York, USA |
|                             NA60 Experiment at CERN, Geneva, Switzerland |
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