| US 7,400,520 B2 | ||
| Low-power CAM | ||
| Gil I. Winograd, Aliso Viejo, Calif. (US); Esin Terzioglu, Aliso Viejo, Calif. (US); and Morteza Cyrus Afghahi, Coto De Caza, Calif. (US) | ||
| Assigned to Norvelics, LLC, Aliso Viejo, Calif. (US) | ||
| Filed on May 10, 2006, as Appl. No. 11/431,439. | ||
| Claims priority of provisional application 60/760255, filed on Jan. 19, 2006. | ||
| Prior Publication US 2007/0165435 A1, Jul. 19, 2007 | ||
| Int. Cl. G11C 15/00 (2006.01) | ||
| U.S. Cl. 365—49.11 [365/49.17; 711/108] | 7 Claims |
| 1. A CAM, comprising;
a plurality of memory cells grouped to store a word,
wherein the memory cells are organized into a plurality of ripple groups, each ripple group's memory cells being configured
to assert a mismatch output if a content for the memory cell mismatches a corresponding bit of a comparand word, and wherein
each ripple group includes:
a NOR gate adapted to NOR the mismatch outputs of the memory cells in its ripple group;
an inverter adapted to invert a NOR output from the NOR gate to provide an OR output representing the logical OR of the ripple
group's mismatch outputs; and
pre-charge circuitry for pre-charging the NOR output to a power supply voltage VDD;
wherein the ripple groups are arranged from a first ripple group to a last ripple group such that a NOR output from the second
ripple group can only be discharged if all the second ripple group's mismatch outputs are false and the first ripple group's
OR output is false, and so on such that a NOR output from the last ripple group can only be discharged if all the last ripple
group's mismatch outputs are false and a next-to-last ripple group's OR output is false.
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