| US 7,388,802 B2 | ||
| Memory protected against attacks by error injection in memory cells selection signals | ||
| Sylvie Wuidart, Pourrieres (France); Mathieu Lisart, Aix En Provence (France); and Nicolas Demange, Saint Maximin la Sainte Baume (France) | ||
| Assigned to STMicroelectronics S.A., Montrouge (France) | ||
| Filed on Jun. 13, 2006, as Appl. No. 11/423,852. | ||
| Claims priority of application No. 05 06034 (FR), filed on Jun. 15, 2005. | ||
| Prior Publication US 2007/0002616 A1, Jan. 04, 2007 | ||
| Int. Cl. G11C 8/00 (2006.01); G11C 5/06 (2006.01); G11C 7/00 (2006.01); G11C 8/02 (2006.01); G06F 12/00 (2006.01) | ||
| U.S. Cl. 365—230.01 [365/63; 365/189.11; 365/230.02; 365/231; 711/220] | 23 Claims |
| 8. A memory, comprising:
memory cells arranged in a memory array;
an address decoder to apply memory cells selection signals to the memory array according to a read address applied to the
memory; and
an address reconstruction circuit to supply a first reconstructed address by reconstruction of at least one part of the read
address from the memory cells selection signals, the address reconstruction circuit including:
at least one group of switches arranged to bias to a first logic state an output node common to the switches, which supplies
a bit of the reconstructed address;
an element to bias the output node by default to a second logic state; and
means for applying the memory cells selection signals to control terminals of the switches.
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