%sub file of vmefpga1, as clock, feb_data and sigle/double frame switch 9/26/00%
subdesign sw_mode           
(    v_add[13..6],         %raw vme address %
     st15,                 
     CLK                    %switched clock%
                      :input;
     clk_sel,              %clock select to muxfpga%
     data_sel,             %data select to muxfpga %
     v_control             %double frame indicator to muxfpga%
                     :output;
)
variable
     clk_sw:  latch;
     C_DELAY:  DFF;
     PH     : DFFE; %gated clock with 1/2 CLK rate% 
     data_sw:  latch;
     frame_sw: latch;
begin
     %single/double frame switch%
frame_sw.ena = st15 & ((v_add[13..11] == 5) # (v_add[13..11] == 6)) ;
frame_sw.d   = (v_add[13..11]==5) & ((v_add[9..6]==5) # (v_add[9..6]==6)
              # (v_add[9..6]==7)) 
            # (v_add[13..11] == 6) & (v_add[9..6]==1); 
V_CONTROL =  frame_sw.q;         %V_CONTROL=1, DOUBLE FRAME%

     %clock switch%
 PH.CLK     = CLK; 
 PH.ENA = (v_add[13..11]==5) # (v_add[13..11]==6);
 PH.D       = !PH.Q;
 CLK_SW.ENA =st15 & !CLK & ((v_add[13..11] == 5) # (v_add[13..11] == 6)) ;
 CLK_SW.D   = (v_add[13..11] == 5) & ((v_add[9..6]   == 1) # (v_add[9..6]==3)
               # (v_add[9..6]==7));
  
 C_DELAY.CLK  = PH.Q;
 C_DELAY.D    = CLK_SW.Q;
 CLK_SEL   =  C_DELAY.Q;          %clk_sel=1, offline is selected%

    %data_sel switch%
 data_sw.ena = st15 & ((v_add[13..11] == 5) # (v_add[13..11] == 6));
 DATA_SW.D   = (v_add[13..11] == 5) &((v_add[9..6]== 2) # (v_add[9..6]== 3)
               # (v_add[9..6]==7)); 
 DATA_SEL   =  DATA_SW.Q;        %data_sel=1, offline is selected%
end;