	US 7,359,168 B2
	Arc fault circuit interrupter and method for disabling series arc protection during current transients
Robert T. Elms, Monroeville, Pa. (US); and Kevin L. Parker, Pittsburgh, Pa. (US)
Assigned to Eaton Corporation, Cleveland, Ohio (US)
Filed on Oct. 18, 2005, as Appl. No. 11/253,193.
Prior Publication US 2007/0086124 A1, Apr. 19, 2007
Int. Cl. H02H 3/16 (2006.01)

U.S. Cl. 361—42 [361/44]

4 Claims

1. An arc fault circuit interrupter for an electrical circuit including a load, said arc fault circuit interrupter comprising:

a line terminal;

a load terminal;

separable contacts electrically connected between said line terminal and said load terminal;

a current sensor structured to sense current associated with said load and flowing between said line terminal and said load terminal and through said separable contacts, said sensed current including a plurality of line cycles;

at least one arc fault detection circuit structured to provide series arc protection and to generate a trip signal responsive to said sensed current from said current sensor, one of said at least one arc fault detection circuit being structured to collect a plurality of samples of said sensed current over said line cycles, determine a single current transient associated with energization of said load, and responsively inhibit said series arc protection;

an operating mechanism structured to open said separable contacts responsive to said trip signal;

wherein said one of said at least one arc fault detection circuit is further structured to determine a first maximum value of said sensed current from one of said line cycles and a second maximum value of said sensed current from the subsequent one of said line cycles, determine if the difference between said first and second maximum values is greater than a first predetermined value and responsively set a first variable to a second predetermined value, and responsively increment a second variable by a third predetermined value; and

wherein said one of said at least one arc fault detection circuit is further structured, for each of said line cycles, to determine if the first variable is greater than zero and to responsively decrement said first variable by a predetermined value.