From owner-nwchem-users@emsl.pnl.gov Thu Jul  6 09:36:01 2006
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Date: Thu, 06 Jul 2006 09:35:04 -0700
From: "Kowalski, Karol" <karol.kowalski@pnl.gov>
Subject: RE: [NWCHEM] TCE and tilesize directive
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This is a very good suggestion. In the next release we will 
put all pertinent information regarding size of the tiles. 
Based on our experience on small machines, it is recommended to 
control size of tiles manually and use "tilesize" values between 10 and
20.
However, for bigger values of tilesize we observe the better performance
of 
the TCE-CC codes.

Best regards,
Karol




-----Original Message-----
From: owner-nwchem-developers@emsl.pnl.gov
[mailto:owner-nwchem-developers@emsl.pnl.gov] On Behalf Of Robert Hinde
Sent: Thursday, July 06, 2006 6:52 AM
To: nwchem-users@emsl.pnl.gov
Subject: [NWCHEM] TCE and tilesize directive

There isn't much in the manual about the tilesize directive.  Is it
possible to give a short tutorial regarding the conditions under which
it should be manually set?  In particular, for those of us stuck with
low-RAM machines (2 or 3 GB) is it a good idea to manually set the
tilesize, and if so, to what?

Thanks,
RJH

Shan-ho Tsai wrote:
> Thanks for all the replies!
> The suggestions made by Karol do indeed solve the problem.
> Thanks again!
> Shan-Ho
> 
> ---- Original message ----
>> Date: Wed, 05 Jul 2006 09:19:30 -0700
>> From: "Kowalski, Karol" <karol.kowalski@pnl.gov>
>> Subject: RE: [NWCHEM] task tce energy - memory allocation error
>> To: Shan-ho Tsai <shtsai@uga.edu>, nwchem <nwchem-users@emsl.pnl.gov>
>>
>> Hi Shan-ho,
>>
>> You may want to consider alternative I/O schemes.
>> Please try to put in the tce group the following directive:
>> "io replicated".
>> Also, in order to control the size of tiles, please define it
>> explicitly:
>> "tilesize 15"
>> This should help.
>> Best regards,
>> Karol