| US 7,362,623 B2 | ||
| Semiconductor memory device | ||
| Mitsuaki Honma, Yokohama (Japan); and Noboru Shibata, Kawasaki (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Feb. 13, 2006, as Appl. No. 11/352,363. | ||
| Claims priority of application No. 2005-090860 (JP), filed on Mar. 28, 2005. | ||
| Prior Publication US 2006/0227602 A1, Oct. 12, 2006 | ||
| Int. Cl. G11C 16/04 (2006.01) | ||
| U.S. Cl. 365—189.09 [365/185.21; 365/205; 365/207] | 11 Claims |
| 1. A semiconductor memory device comprising:
a memory cell array having a plurality of memory cells arranged therein; and
a sense amplifier circuit configured to read data of the memory cell array, wherein
a comparison operation is performed between read out data from the memory cell array and externally supplied expectance data
in the sense amplifier circuit, wherein
the sense amplifier circuit includes a plurality of sense units for storing page read data and page expectance data, and the
page read data and the page expectance data are subjected to the comparison operation in a lump in the sense amplifier circuit,
the page read data being defined as a set of data bits, which are simultaneously read from plural memory cells.
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