| US 7,406,586 B2 | ||
| Fetch and dispatch disassociation apparatus for multi-streaming processors | ||
| Mario Nemirovsky, Saratoga, Calif. (US); Adolfo Nemirovsky, San Jose, Calif. (US); Narendra Sankar, Campbell, Calif. (US); and Enrique Musoll, San Jose, Calif. (US) | ||
| Assigned to MIPS Technologies, Inc., Mountain View, Calif. (US) | ||
| Filed on Oct. 06, 2006, as Appl. No. 11/539,322. | ||
| Application 11/539322 is a continuation of application No. 09/706154, filed on Nov. 03, 2000, granted, now 7,139,898. | ||
| Prior Publication US 2007/0260852 A1, Nov. 08, 2007 | ||
| Int. Cl. G06F 9/30 (2006.01) | ||
| U.S. Cl. 712—215 | 20 Claims |
| 1. A pipelined multistreaming processor, comprising:
an instruction cache configured to concurrently provide a plurality of instructions for a plurality of instruction streams;
fetch logic coupled to the instruction cache configured to concurrently fetch said plurality of instructions for the plurality
of instruction streams from the instruction cache, wherein said plurality of instructions includes at least two instructions
for a first instruction stream of the plurality of instruction streams;
a plurality of instruction queues coupled to the fetch logic wherein each one of the plurality of instruction queues is associated
with at least one of the plurality of instruction streams, wherein the number of the plurality of instruction queues is greater
than the plurality of instruction streams that are provided by the instruction cache;
a dispatch stage coupled to the plurality of instruction queues and configured to select and dispatch instructions for the
plurality of instruction streams.
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