%vmefpga is used on vme4dsp test module epf10k30eqc208-2 feb. 23, 2000% %REV3/VMEFPGA IS REVISED TO ADD FEB_PORT3 with LPM_RAM_DP 5/18/00% %ADD TTC_PORT3 6/7/00% %modify fifo_port.tdf to remove S3(read null) state 7/28/00% %modified for vem4dsp v2 board 10/5/00 % FUNCTION VME_PORT4 (CLK,/SYSRST,V_ADD[17..6],V_WORD,V_/DS,V_/WRITE,PUREADBACK[31..0], FIFOREADBACK[31..0], FEB_STATUS[31..0],BSY[4..1]) RETURNS (VMEDATAIN[31..0], VMEADD[13..6],DTACK,R/W,DIRTRANS,/TRAN_OE, VME_/RST, ST[15..0], VBUS_DATA[31..0]); FUNCTION PU_PORT2 (CLK,/RESET,VMEADD[13..6],VMEDATAIN[31..0],VME_R/W,ST[5],PU_RDY) RETURNS (PU_READBACK[31..0],ADD[3..0],R/W,/CS,/RST,PU_BSY,PU_/DS,PU_DAT[7..0]); FUNCTION FIFO_PORT1 (CLK,/RST,DI[31..0],FIFO_EVTRDY,VMEADD[13..6],ST6,ST7,ST8,ST15) RETURNS(FIFO_EVTEND,/REN,/OE,BSY,DO[31..0]); FUNCTION FEB_PORT_new1(CLK, /RST,VMEADD[13..6], DI[31..0],ST10,ST9,st6,double,mux_r_bsy) RETURNS (DO[15..0], BSY, FEB_STATUS[31..0], muxload, muxsend, TFLAG); FUNCTION TTC_PORT3(CLK, /RST, DI[31..0], VMEADD[13..6], ST5, TTC_FLG) RETURNS (TTC_DAT[7..0], TTC_BCIDWR, TTC_TYPEWR, TTC_RSTN, FEB_FLG,BSY); FUNCTION SW_MODE (CLK,V_ADD[13..6],ST15) RETURNS (CLK_SEL, DATA_SEL, V_CONTROL); subdesign vmefpga2 ( %VME BUS % clk, %40 mhz system clock from on board oscilator% v_a[17..6], %vme address% v_word, %module/signal recongnition% v_/sysrst, %vme reset% v_/write, %vme /write% v_/ds %vme data strobe% :input; v_dat[31..0] %vme data% : bidir; dtack_v, %dtack to vme% t1_/oe, %the output enable for top transceiver% t2_/oe, %the output enable for bottom transceiver% dir_1, %the direction for top transceiver% dir_2 %the direction for bottom transceiver% : output; %PU_VME PORT% PU_RDY :INPUT; PU_R/W, % % PU_/CS, PU_/RST, PU_ADD[3..0] :OUTPUT; PU_DSN, PU_D[7..0] : BIDIR; %fifo output port% FIFO_DI[31..0], %FIFO OUTPUT DATA% FIFO_EVTRDY %FIFO_EVTRDY FLAG FROM OUTFPGA% :INPUT; FIFO_/REN, % READ ENABLE TO FIFO% FIFO_/OE, % OUTPUT ENABLE TO FIFO% FIFO_EVTEND % PULSE TO OUTFPGA THAT EVENT READ IS COMPLETED% :OUTPUT; %FEB_port% busy, pu_irq1, pu_irq2, %reserved inputs from input connector on PU module% mux_r_bsy %feb data read busy, from muxfpga, new 10/5/2000% :input; FEB_LINKST, %used as muxload% FEB_LINKRST, %used as muxsend% FEB_DO[15..0] %FEB DATA BLOCK TO INPUTFPGA% :OUTPUT; %TTC OUTPUT% TTC_DAT[7..0], %TTC DATA TO INPUTFPGA% TTC_TYPE, TTC_BCID, TTC_RSTN %UNUSED, ASSIGN TO VCC ?% :OUTPUT; %vme control to mux fpga% M_/CLR, %VME CLEAR TO MUX FPGA% V_CONTROL, %A SPARE VME CONTROL TO MUX FPGA% CLK_SEL, %EXT OR LOCAL TTC CLOCK SELECT% DATA_SEL, %ONLINE OR VME TEST FEB DATA SELECT% EN_3V_PU %ENABLE CONTROL TO 3.3V REGULATOR, TIED TO HIGH % :OUTPUT; ) VARIABLE PU :PU_PORT2; FO :FIFO_PORT1; %new, 7/28/00% FEB :FEB_PORT_new1; %new 10/5/2000 % TTC :TTC_PORT3; V :vme_port4; SW :SW_MODE; %NEW, MODE SWITCH, 9/26/00% begin %assign connections for vme_port% v.clk = CLK; V./SYSRST = V_/SYSRST; V.V_ADD[17..6] = V_A[17..6]; V.V_WORD = V_WORD; V.V_/DS = V_/DS; V.V_/WRITE = V_/WRITE; v.bsy[1] = PU.PU_BSY; %PU_PORT IS BUSY% V.BSY[2] = FO.BSY; %FIFO_PORT IS BUSY% V.BSY[3] = FEB.BSY; %FEB_PORT IS BUSY% V.BSY[4] = TTC.BSY; %TTC_PORT IS BUSY% V_DAT[31..0] = V.VBUS_DATA[31..0]; %BIR VME DATA% V.PUREADBACK[31..0] = PU.PU_READBACK[31..0]; V.FIFOREADBACK[31..0] = FO.DO[31..0]; V.FEB_STATUS[31..0] = FEB.FEB_STATUS[31..0]; %5/11/00% DTACK_V = V.DTACK; t1_/oe = V./TRAN_OE; t2_/oe = V./TRAN_OE; DIR_1 = V.DIRTRANS; DIR_2 = V.DIRTRANS; %INTERFACING PU% PU.CLK = CLK; PU./RESET = V.VME_/RST;%VME_PORT.TDF ISSSUE RESET FOR OTHER PART OF FPGA% PU.VMEADD[13..6] = V.VMEADD[13..6]; PU.VMEDATAIN[31..0] = V.VMEDATAIN[31..0]; PU.VME_R/W = V.R/W; PU.ST[5] =V.ST[5]; PU.PU_RDY = PU_RDY; PU_DSN = PU.PU_/DS; PU_D[7..0] = PU.PU_DAT[7..0]; PU_ADD[3..0] = PU.ADD[3..0]; PU_R/W = PU.R/W; PU_/CS = PU./CS; PU_/RST = PU./RST; %INTERFACING FIFO% FO.CLK = CLK; FO./RST = V.VME_/RST; FO.DI[31..0] = FIFO_DI[31..0]; FO.FIFO_EVTRDY = FIFO_EVTRDY; FO.VMEADD[13..6] = V.VMEADD[13..6]; FO.ST6 = V.ST[6]; FO.ST7 = V.ST[7]; FO.ST8 = V.ST[8]; FO.ST15 = V.ST[15]; FIFO_EVTEND = FO.FIFO_EVTEND; FIFO_/REN = FO./REN; FIFO_/OE = FO./OE; %INTERCING FEB_PORT% FEB.CLK = CLK; FEB./RST = V.VME_/RST; FEB.VMEADD[13..6] = V.VMEADD[13..6]; FEB.DI[31..0] = V.VMEDATAIN[31..0]; FEB.ST[10..9] = V.ST[10..9]; FEB.ST[6] = V.ST[6]; FEB.MUX_R_BSY = mux_r_bsy; FEB.double = v_control; FEB_DO[15..0] = FEB.DO[15..0]; FEB_LINKST = feb.muxload; FEB_LINKRST = feb.muxsend; %INTERFACING TTC_PORT, NOT IMPLEMENTED 5/11/00% TTC.CLK = CLK; TTC./RST = V.VME_/RST; TTC.VMEADD[13..6] = V.VMEADD[13..6]; TTC.DI[31..0] = V.VMEDATAIN[31..0]; TTC.ST5 = V.ST[5]; TTC.TTC_FLG = FEB.TFLAG; TTC_DAT[7..0] = TTC.TTC_DAT[7..0]; TTC_TYPE = TTC.TTC_TYPEWR; TTC_BCID = TTC.TTC_BCIDWR; TTC_RSTN = TTC.TTC_RSTN; %CLOCK, DATA SWITCH AND FRAME MODE SELECTION TO MUX FPGA, 9/26/00% SW.CLK = CLK; SW.ST15 = V.ST15; SW.V_ADD[13..6] = V_A[13..6]; CLK_SEL = SW.CLK_SEL; DATA_SEL = SW.DATA_SEL; V_CONTROL = SW.V_CONTROL; M_/CLR = V.VME_/RST & !(V_A[13..11]==5) & !(V_A[13..11]==6); EN_3V_PU = VCC; END;