In addressing NASA’s planetary robotic and distributed sensor network needs, a low-power, silicon-on-insulator (SOI) complementary metal-oxide semiconductor (CMOS) transceiver chip has been successfully designed, fabricated, and demonstrated for use in energy-efficient, reliable, miniaturized wireless radiofrequency (RF) communications systems. The receiver supports a wide range of data rates (0.1 to 100 kilobits per second, kbps). A team led by North Carolina A&T State University, with coinvestigators at North Carolina State University and the Jet Propulsion Laboratory, worked closely with the NASA Glenn Research Center in accomplishing this effort.
Low-power UHF SOI CMOS receiver circuit. SAW, surface acoustic wave; LNA, low-noise amplifier; LPF, low-pass filter; IFA, intermediate frequency amplifier; A/D, analog-to-digital converter; L, decimation rate; T, symbol period; sgn, signum function (sgn = 1 when > 0, sgn = 0 when ≤ 0); Qn, quadrature signal at the output of the accumulator; Decim, decimator; Accum, accumulator.
Long description of figure 1.
Future Mars missions will require low-power, radiation-hardened ultra-high-frequency (UHF) receivers for orbiter-lander communication. To meet these requirements, Honeywell’s 0.35-μm SOI CMOS process was chosen for the design and implementation of a UHF single-chip receiver (see the block diagram). The SOI CMOS process provides high-quality passives such as spiral inductors, resistors, and capacitors. The buried oxide layer and semi-insulating substrate provide excellent isolation between digital and analog circuit blocks (mixed-signal circuits). The device-to-device isolation is similar to that of gallium arsenide but is achievable at a lower cost.
Final prototype receiver chip.
A prototype single-chip receiver (see the photomicrograph) was designed at a frequency of 435 MHz with a maximum gain measured at 85 dB, a cascaded noise figure of 5.2 dB, and a current dissipation of 21 mA at 3 V. The UHF band was selected because it has been designated as a forward-link spectrum allocation from a Mars relay satellite to surface and orbital user assets. This architecture is particularly good for applications in the presence of strong random Doppler frequency shift because the receiver circuit is targeted to address needs for an orbiter-lander communication system around Mars. For data rates on the order of 100 kbps or less, orbital analysis indicates thatthe Doppler shift is significant enough to require compensation. The double-differential phase-shift-keying (DDPSK) receiver circuit was invariant to frequency offset because of the use of a double-differential technique. This resulted in a simplified circuit implementation, thereby saving power.
A number of circuits and components were designed and tested including low-noise amplifiers; double-balanced in-phase and quadrature mixers; image reject intermediate-frequency bandpass active filters; DDPSK baseband circuits, a bandgap reference circuit; voltage-controlled oscillators at 435, 870, and 1740 MHz; and phase-lock loop circuits to generate quadrature local oscillator signals. These designs are now available for use as reference circuits for future low-power transceiver implementations. Twelve receiver chips in 88-pin carriers were completed in the final chip development effort. The low-power, SOI CMOS transceiver chip was successfully developed and tested under a grant to North Carolina A&T State University in Greensboro, North Carolina, and managed by Glenn.
Dogan, Numan, S.: Advanced Low-Power Silicon on Insulator (SOI) Complimentary Metal Oxide Silicon (CMOS) Transceiver for Distributed Sensor Networks; Progress Report. NASA Grant Number NAG3-2584, 2005. Available from the NASA Center for Aerospace Information.
Glenn contact: Gene Fujikawa, 216-433-3495, Gene.Fujikawa@nasa.govLast updated: September 6, 2007
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