#include <vxWorks.h>
#include <vxLib.h>
#include "mv5500/config.h"
#include "vme.h"
#include "ecdr814gcDrv.h"
Include dependency graph for ecdr814gcIoctl.cpp:
Go to the source code of this file.
Functions | |
STATUS | ecdr814gcIoctl (ECDR814_DEV_HANDLE ecdr814Dev, INT32 requestCode, INT32 arg) |
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Definition at line 10 of file ecdr814gcIoctl.cpp. References DMA_TRANSFER_INFO_BLK::Byte_Cnt, CHANNEL_0_DONE_INT, CHANNEL_0_INT_ENABLE, CHANNEL_0_TRIG_CNT_INT, CHANNEL_1_DONE_INT, CHANNEL_1_INT_ENABLE, CHANNEL_1_TRIG_CNT_INT, CHANNEL_2_DONE_INT, CHANNEL_2_INT_ENABLE, CHANNEL_2_TRIG_CNT_INT, CHANNEL_3_DONE_INT, CHANNEL_3_INT_ENABLE, CHANNEL_3_TRIG_CNT_INT, CHANNEL_4_DONE_INT, CHANNEL_4_INT_ENABLE, CHANNEL_4_TRIG_CNT_INT, CHANNEL_5_DONE_INT, CHANNEL_5_INT_ENABLE, CHANNEL_5_TRIG_CNT_INT, CHANNEL_6_DONE_INT, CHANNEL_6_INT_ENABLE, CHANNEL_6_TRIG_CNT_INT, CSR_MASK, DMA_TRANSFER_INFO_BLK::DescriptorAddr, DMA_TRANSFER_INFO_BLK::Direction, DMA_CHAIN, DMA_ChainTransfer(), DMA_DESC_OFFSET, DMA_INT_WHEN_DONE, DMA_INT_WHEN_LERR, DMA_START, DMA_TransferGo(), ECDR814_CHECK, ECDR814_CLEAR, ECDR814_DISABLE, ECDR814_DMA_CHAIN, ECDR814_GET_BYTE_COUNT, ECDR814_GET_CHANNEL, ECDR814_GET_DATA_MODE, ECDR814_GET_NUM_BITS, ECDR814_GET_NUM_SUB_CHANNELS, ECDR814_GET_TRANSFER_TYPE, ECDR814_HEADER_TEST, ECDR814_MODIFY_WORD_COUNT, ECDR814_PROGRAM_ALL_CHANNELS, ECDR814_PROGRAM_CHANNEL, ECDR814_PROGRAM_FLASH, ECDR814_PROGRAM_PLLS, ECDR814_READ_INI_FILE, ECDR814_RELEASE, ECDR814_RESET, ECDR814_SELECT_NOTIFICATION, ECDR814_SET_BUFFER, ECDR814_SET_CHANNEL, ECDR814_SET_NUM_TRIGS, ECDR814_SHOW, ECDR814_SHOW_PROGRAM_INFO, ECDR814_START, ECDR814_STOP, ECDR814_TEST_FLASH, ECDR814_TRIG, ECDR814_VERIFY_FLASH, ecdr814gcDisableISRs(), ecdr814gcEnableISRs(), ecdr814gcInstallISR(), ecdr814gcProgramGray(), ecdr814gcProgramPlls(), ecdr814gcReadbackGray(), ecdr814gcReFlash(), ecdr814gcScanFile(), ecdr814gcTestFlash(), ecdr814gcVerifyFlash(), ENABLE_FLASH_ADDRESS, FLASH_SELECT_01, FLASH_SELECT_23, FLASH_SELECT_45, FLASH_SELECT_67, Key_Hit(), DMA_TRANSFER_INFO_BLK::Loc_Addr, DMA_TRANSFER_INFO_BLK::Mem_Addr, SRAM_POINTER_0_RESET, SRAM_POINTER_1_RESET, SRAM_POINTER_2_RESET, SRAM_POINTER_3_RESET, DMA_TRANSFER_INFO_BLK::Transfer_Type, UNI_VME_INT_DMA_DONE, UNI_VME_INT_LINT0, UNI_VME_INT_LINT1, UNI_VME_INT_LINT2, UNI_VME_INT_LINT3, UNI_VME_INT_LINT4, UNI_VME_INT_LINT5, UNI_VME_INT_LINT6, UNI_VME_INT_LINT7, and UniverseII_Reset(). Referenced by ecdr814gcDevCreate(), ecdr814gcDrv(), and ecdr814gcRead(). 00011 { 00012 DMA_TRANSFER_INFO_BLK DmaXfer[ECDR814_MAX_DMAS]; 00013 INT32 i; 00014 INT32 channel; 00015 INT32 subChannel; 00016 INT32 pair; 00017 INT32 intStat; 00018 INT32 j; 00019 INT32 k; 00020 INT32 l; 00021 INT32 trigs; 00022 INT32 trigType; 00023 INT32 numChans; 00024 INT32 subChannelInfo[2]; 00025 INT32 wordCount; 00026 INT32 useChan; 00027 INT32 pattern[36] = { 0x00000000, 0xFFFFFFFF, 0xAAAAAAAA, 0x55555555, 00028 0x00000001, 0x00000002, 0x00000004, 0x00000008, 00029 0x00000010, 0x00000020, 0x00000040, 0x00000080, 00030 0x00000100, 0x00000200, 0x00000400, 0x00000800, 00031 0x00001000, 0x00002000, 0x00004000, 0x00008000, 00032 0x00010000, 0x00020000, 0x00040000, 0x00080000, 00033 0x00100000, 0x00200000, 0x00400000, 0x00800000, 00034 0x01000000, 0x02000000, 0x04000000, 0x08000000, 00035 0x10000000, 0x20000000, 0x40000000, 0x80000000 }; 00036 00037 if(!ecdr814Dev->Is_Open) 00038 { 00039 printf("\necdr814gcIoctl: Device is not opened\n"); 00040 return EC_ERROR; 00041 } 00042 switch(requestCode) 00043 { 00044 case ECDR814_CHECK: 00045 printf("ECDR814_CHECK\n");taskDelay(1); 00046 if(ecdr814Dev->notification == ECDR814_SEM_DATA) 00047 { 00048 semTake(ecdr814Dev->collection0DoneSem, WAIT_FOREVER); 00049 semTake(ecdr814Dev->collection1DoneSem, WAIT_FOREVER); 00050 semTake(ecdr814Dev->collection2DoneSem, WAIT_FOREVER); 00051 semTake(ecdr814Dev->collection3DoneSem, WAIT_FOREVER); 00052 semTake(ecdr814Dev->collection4DoneSem, WAIT_FOREVER); 00053 semTake(ecdr814Dev->collection5DoneSem, WAIT_FOREVER); 00054 semTake(ecdr814Dev->collection6DoneSem, WAIT_FOREVER); 00055 semTake(ecdr814Dev->collection7DoneSem, WAIT_FOREVER); 00056 } 00057 else 00058 { 00059 while((UINT32)ecdr814Dev->hUniverseII->VINT_STAT != (UINT32)0xFF000000) 00060 ; 00061 ecdr814Dev->hUniverseII->VINT_STAT = 0xFF000000; 00062 } 00063 break; 00064 00065 case ECDR814_CLEAR: 00066 ecdr814Dev->hECDR814->CSR = (0x000001FF & ecdr814Dev->hSetup->ecdr814Info.CSR) & ~ENABLE_EXT_SYNC; 00067 00068 ecdr814Dev->hChannelPairHandle[0]->CSR1 = (ecdr814Dev->hChannelPairHandle[0]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_0_RESET | PLL_RESET_RELEASE; 00069 ecdr814Dev->hChannelPairHandle[0]->CSR1 = (ecdr814Dev->hChannelPairHandle[0]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_1_RESET | PLL_RESET_RELEASE; 00070 ecdr814Dev->hChannelPairHandle[0]->CSR1 = (ecdr814Dev->hChannelPairHandle[0]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_2_RESET | PLL_RESET_RELEASE; 00071 ecdr814Dev->hChannelPairHandle[0]->CSR1 = (ecdr814Dev->hChannelPairHandle[0]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_3_RESET | PLL_RESET_RELEASE; 00072 ecdr814Dev->hChannelPairHandle[0]->CSR2 = (ecdr814Dev->hChannelPairHandle[0]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_0_RESET | PLL_RESET_RELEASE; 00073 ecdr814Dev->hChannelPairHandle[0]->CSR2 = (ecdr814Dev->hChannelPairHandle[0]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_1_RESET | PLL_RESET_RELEASE; 00074 ecdr814Dev->hChannelPairHandle[0]->CSR2 = (ecdr814Dev->hChannelPairHandle[0]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_2_RESET | PLL_RESET_RELEASE; 00075 ecdr814Dev->hChannelPairHandle[0]->CSR2 = (ecdr814Dev->hChannelPairHandle[0]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_3_RESET | PLL_RESET_RELEASE; 00076 ecdr814Dev->hChannelPairHandle[1]->CSR1 = (ecdr814Dev->hChannelPairHandle[1]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_0_RESET | PLL_RESET_RELEASE; 00077 ecdr814Dev->hChannelPairHandle[1]->CSR1 = (ecdr814Dev->hChannelPairHandle[1]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_1_RESET | PLL_RESET_RELEASE; 00078 ecdr814Dev->hChannelPairHandle[1]->CSR1 = (ecdr814Dev->hChannelPairHandle[1]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_2_RESET | PLL_RESET_RELEASE; 00079 ecdr814Dev->hChannelPairHandle[1]->CSR1 = (ecdr814Dev->hChannelPairHandle[1]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_3_RESET | PLL_RESET_RELEASE; 00080 ecdr814Dev->hChannelPairHandle[1]->CSR2 = (ecdr814Dev->hChannelPairHandle[1]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_0_RESET | PLL_RESET_RELEASE; 00081 ecdr814Dev->hChannelPairHandle[1]->CSR2 = (ecdr814Dev->hChannelPairHandle[1]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_1_RESET | PLL_RESET_RELEASE; 00082 ecdr814Dev->hChannelPairHandle[1]->CSR2 = (ecdr814Dev->hChannelPairHandle[1]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_2_RESET | PLL_RESET_RELEASE; 00083 ecdr814Dev->hChannelPairHandle[1]->CSR2 = (ecdr814Dev->hChannelPairHandle[1]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_3_RESET | PLL_RESET_RELEASE; 00084 ecdr814Dev->hChannelPairHandle[2]->CSR1 = (ecdr814Dev->hChannelPairHandle[2]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_0_RESET | PLL_RESET_RELEASE; 00085 ecdr814Dev->hChannelPairHandle[2]->CSR1 = (ecdr814Dev->hChannelPairHandle[2]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_1_RESET | PLL_RESET_RELEASE; 00086 ecdr814Dev->hChannelPairHandle[2]->CSR1 = (ecdr814Dev->hChannelPairHandle[2]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_2_RESET | PLL_RESET_RELEASE; 00087 ecdr814Dev->hChannelPairHandle[2]->CSR1 = (ecdr814Dev->hChannelPairHandle[2]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_3_RESET | PLL_RESET_RELEASE; 00088 ecdr814Dev->hChannelPairHandle[2]->CSR2 = (ecdr814Dev->hChannelPairHandle[2]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_0_RESET | PLL_RESET_RELEASE; 00089 ecdr814Dev->hChannelPairHandle[2]->CSR2 = (ecdr814Dev->hChannelPairHandle[2]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_1_RESET | PLL_RESET_RELEASE; 00090 ecdr814Dev->hChannelPairHandle[2]->CSR2 = (ecdr814Dev->hChannelPairHandle[2]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_2_RESET | PLL_RESET_RELEASE; 00091 ecdr814Dev->hChannelPairHandle[2]->CSR2 = (ecdr814Dev->hChannelPairHandle[2]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_3_RESET | PLL_RESET_RELEASE; 00092 ecdr814Dev->hChannelPairHandle[3]->CSR1 = (ecdr814Dev->hChannelPairHandle[3]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_0_RESET | PLL_RESET_RELEASE; 00093 ecdr814Dev->hChannelPairHandle[3]->CSR1 = (ecdr814Dev->hChannelPairHandle[3]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_1_RESET | PLL_RESET_RELEASE; 00094 ecdr814Dev->hChannelPairHandle[3]->CSR1 = (ecdr814Dev->hChannelPairHandle[3]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_2_RESET | PLL_RESET_RELEASE; 00095 ecdr814Dev->hChannelPairHandle[3]->CSR1 = (ecdr814Dev->hChannelPairHandle[3]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_3_RESET | PLL_RESET_RELEASE; 00096 ecdr814Dev->hChannelPairHandle[3]->CSR2 = (ecdr814Dev->hChannelPairHandle[3]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_0_RESET | PLL_RESET_RELEASE; 00097 ecdr814Dev->hChannelPairHandle[3]->CSR2 = (ecdr814Dev->hChannelPairHandle[3]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_1_RESET | PLL_RESET_RELEASE; 00098 ecdr814Dev->hChannelPairHandle[3]->CSR2 = (ecdr814Dev->hChannelPairHandle[3]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_2_RESET | PLL_RESET_RELEASE; 00099 ecdr814Dev->hChannelPairHandle[3]->CSR2 = (ecdr814Dev->hChannelPairHandle[3]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_3_RESET | PLL_RESET_RELEASE; 00100 EIEIO_SYNC; 00101 00102 semTake(ecdr814Dev->collection0DoneSem, NO_WAIT); 00103 semTake(ecdr814Dev->collection1DoneSem, NO_WAIT); 00104 semTake(ecdr814Dev->collection2DoneSem, NO_WAIT); 00105 semTake(ecdr814Dev->collection3DoneSem, NO_WAIT); 00106 semTake(ecdr814Dev->collection4DoneSem, NO_WAIT); 00107 semTake(ecdr814Dev->collection5DoneSem, NO_WAIT); 00108 semTake(ecdr814Dev->collection6DoneSem, NO_WAIT); 00109 semTake(ecdr814Dev->collection7DoneSem, NO_WAIT); 00110 semTake(ecdr814Dev->transferDoneSem, NO_WAIT); 00111 semTake(ecdr814Dev->releaseSem, NO_WAIT); 00112 ecdr814Dev->Is_Busy=0; 00113 00114 intStat = ecdr814Dev->hECDR814->INTSRC; 00115 break; 00116 00117 case ECDR814_DISABLE: 00118 ecdr814Dev->hECDR814->CSR = (CSR_MASK & ecdr814Dev->hSetup->ecdr814Info.CSR) & ~ENABLE_EXT_SYNC; 00119 break; 00120 00121 case ECDR814_DMA_CHAIN: 00122 for(i = 0; i < 8; i++) 00123 { 00124 subChannelInfo[0] = i; 00125 subChannelInfo[1] = (INT32)&numChans; 00126 ecdr814gcIoctl(ecdr814Dev, ECDR814_GET_NUM_SUB_CHANNELS, (int)subChannelInfo); 00127 if((i % 2) == 0) 00128 { 00129 wordCount = (ecdr814Dev->hSetup->channelPairInfo[i / 2].DWS1 & 0x1FFFF) + 1; 00130 } 00131 else 00132 { 00133 wordCount = (ecdr814Dev->hSetup->channelPairInfo[i / 2].DWS2 & 0x1FFFF) + 1; 00134 } 00135 for(j = 0; j < numChans; j++) 00136 { 00137 useChan = j; 00138 if(numChans == 2) 00139 useChan = useChan * 2; 00140 if(ecdr814Dev->hSetup->transferType == SINGLE_READ_TRANSFER) 00141 { 00142 for(k = 0; k < (INT32)((wordCount * trigs) / numChans); k++) 00143 { 00144 ((UINT32 *)ecdr814Dev->hSetup->buffers[i][useChan])[k] = ((UINT32 00145 *)ecdr814Dev->mappedFifos[i][useChan])[k]; 00146 } 00147 } 00148 else 00149 { 00150 DmaXfer[(i * numChans) + useChan].Mem_Addr = (long)ecdr814Dev->hSetup->buffers[i][useChan]; 00151 DmaXfer[(i * numChans) + useChan].Loc_Addr = (long)ecdr814Dev->unmappedFifos[i][useChan]; 00152 DmaXfer[(i * numChans) + useChan].Byte_Cnt = (wordCount * 4 * trigs) / numChans; 00153 DmaXfer[(i * numChans) + useChan].Transfer_Type = ecdr814Dev->hSetup->vmeDmaType; 00154 DmaXfer[(i * numChans) + useChan].Direction = DMA_XFER_PCI_TO_VME; 00155 DmaXfer[(i * numChans) + useChan].DescriptorAddr = (long)(ecdr814Dev->hDmaDescriptors + ((i * 00156 numChans) + useChan) * 8); 00157 } 00158 } 00159 } 00160 if(ecdr814Dev->hSetup->transferType != SINGLE_READ_TRANSFER) 00161 { 00162 DMA_ChainTransfer((DMA_TRANSFER_INFO_BLK **)&DmaXfer, 8); 00163 ecdr814Dev->hECDR814->LDCPP = DMA_DESC_OFFSET; 00164 ecdr814Dev->hECDR814->LDGCS = DMA_START | DMA_CHAIN | DMA_INT_WHEN_DONE | DMA_INT_WHEN_LERR; 00165 DMA_TransferGo(ecdr814Dev->hUniverseII, DMA_DESC_OFFSET, DMA_START | DMA_CHAIN | DMA_INT_WHEN_DONE | DMA_INT_WHEN_LERR); 00166 if(ecdr814Dev->notification == ECDR814_SEM_DMA) 00167 semTake(ecdr814Dev->transferDoneSem, WAIT_FOREVER); 00168 else 00169 { 00170 while(ecdr814Dev->hUniverseII->VINT_STAT != DMA_DONE) 00171 ; 00172 ecdr814Dev->hUniverseII->VINT_STAT = DMA_DONE; 00173 } 00174 } 00175 break; 00176 00177 case ECDR814_GET_BYTE_COUNT: 00178 channel = ((INT32 *)arg)[0]; 00179 if((channel % 2) == 0) 00180 { 00181 *(INT32 *)((INT32 *)arg)[1] = ((ecdr814Dev->hSetup->channelPairInfo[channel / 2].DWS1 & 0x1FFFF) + 1) * 4; 00182 } 00183 else 00184 { 00185 *(INT32 *)((INT32 *)arg)[1] = ((ecdr814Dev->hSetup->channelPairInfo[channel / 2].DWS2 & 0x1FFFF) + 1) * 4; 00186 } 00187 break; 00188 00189 case ECDR814_GET_CHANNEL: 00190 *(INT32 *)arg = ecdr814Dev->hSetup->channel; 00191 break; 00192 00193 case ECDR814_GET_DATA_MODE: 00194 if((ecdr814Dev->hSetup->channel % 2) == 0) 00195 *(INT32 *)arg = ecdr814Dev->hSetup->channelPairInfo[ecdr814Dev->hSetup->channel / 2].CSR1 & UNPACKED_DATA; 00196 else 00197 *(INT32 *)arg = ecdr814Dev->hSetup->channelPairInfo[ecdr814Dev->hSetup->channel / 2].CSR2 & UNPACKED_DATA; 00198 break; 00199 00200 case ECDR814_GET_NUM_BITS: 00201 channel = ((INT32 *)arg)[0]; 00202 if((channel % 2) == 0) 00203 { 00204 if((ecdr814Dev->hSetup->channelPairInfo[channel / 2].DATA_SEL1 & PACK_8_BIT) == PACK_8_BIT) 00205 *(INT32 *)((INT32 *)arg)[1] = EIGHT_BIT; 00206 else 00207 *(INT32 *)((INT32 *)arg)[1] = SIXTEEN_BIT; 00208 } 00209 else 00210 { 00211 if((ecdr814Dev->hSetup->channelPairInfo[channel / 2].DATA_SEL2 & PACK_8_BIT) == PACK_8_BIT) 00212 *(INT32 *)((INT32 *)arg)[1] = EIGHT_BIT; 00213 else 00214 *(INT32 *)((INT32 *)arg)[1] = SIXTEEN_BIT; 00215 } 00216 break; 00217 00218 case ECDR814_GET_NUM_SUB_CHANNELS: 00219 channel = ((INT32 *)arg)[0]; 00220 if((channel % 2) == 0) 00221 { 00222 if((ecdr814Dev->hChannelPairHandle[channel / 2]->CSR1 & GC_4_CHAN) == GC_4_CHAN) 00223 *(INT32 *)((INT32 *)arg)[1] = FOUR_CHANNELS; 00224 else if((ecdr814Dev->hChannelPairHandle[channel / 2]->CSR1 & GC_2_CHAN) == GC_2_CHAN) 00225 *(INT32 *)((INT32 *)arg)[1] = TWO_CHANNELS; 00226 else 00227 *(INT32 *)((INT32 *)arg)[1] = ONE_CHANNEL; 00228 } 00229 else 00230 { 00231 if((ecdr814Dev->hChannelPairHandle[channel / 2]->CSR2 & GC_4_CHAN) == GC_4_CHAN) 00232 *(INT32 *)((INT32 *)arg)[1] = FOUR_CHANNELS; 00233 else if((ecdr814Dev->hChannelPairHandle[channel / 2]->CSR2 & GC_2_CHAN) == GC_2_CHAN) 00234 *(INT32 *)((INT32 *)arg)[1] = TWO_CHANNELS; 00235 else 00236 *(INT32 *)((INT32 *)arg)[1] = ONE_CHANNEL; 00237 } 00238 break; 00239 00240 case ECDR814_GET_TRANSFER_TYPE: 00241 *(INT32 *)arg = ecdr814Dev->hSetup->transferType; 00242 break; 00243 00244 case ECDR814_HEADER_TEST: 00245 printf("Hit a key to trigger\n"); 00246 while(!Key_Hit()); 00247 ecdr814Dev->hECDR814->CSR = (CSR_MASK & ecdr814Dev->hSetup->ecdr814Info.CSR) | SW_SYNC_PULSE; 00248 printf("HEAD0 REGISTER %08x\n", ecdr814Dev->hECDR814->HEAD0); 00249 printf("HEAD1 REGISTER %08x\n", ecdr814Dev->hECDR814->HEAD1); 00250 printf("HEAD0 SRAM %08x\n", *(int *)ecdr814Dev->hFIFOH0); 00251 printf("HEAD1 SRAM %08x\n", *(int *)ecdr814Dev->hFIFOH1); 00252 break; 00253 00254 case ECDR814_MODIFY_WORD_COUNT: 00255 ecdr814Dev->hSetup->wordCount = (INT32)arg; 00256 break; 00257 00258 case ECDR814_PROGRAM_ALL_CHANNELS: 00259 // ecdr814Dev->hECDR814->CSR = ecdr814Dev->hSetup->ecdr814Info.CSR; 00260 ecdr814Dev->hECDR814->CSR = ecdr814Dev->hSetup->ecdr814Info.CSR & ~ENABLE_EXT_SYNC; // DHZ disable external trigger 00261 taskDelay(1); 00262 for(i = 0; i < 4; i++) 00263 ecdr814gcProgramGray(ecdr814Dev->hChannelPairHandle[i], &(ecdr814Dev->hSetup->channelPairInfo[i]), 2); 00264 break; 00265 00266 case ECDR814_PROGRAM_CHANNEL: 00267 channel = arg; 00268 // ecdr814Dev->hECDR814->CSR = ecdr814Dev->hSetup->ecdr814Info.CSR; 00269 ecdr814Dev->hECDR814->CSR = ecdr814Dev->hSetup->ecdr814Info.CSR & ~ENABLE_EXT_SYNC; // DHZ disable external trigger 00270 taskDelay(1); 00271 ecdr814gcProgramGray(ecdr814Dev->hChannelPairHandle[channel / 2], &(ecdr814Dev->hSetup->channelPairInfo[channel / 2]), channel % 2); 00272 break; 00273 00274 case ECDR814_PROGRAM_FLASH: 00275 pair = ((INT32 *)arg)[0]; 00276 switch(pair) 00277 { 00278 case 0: 00279 printf("ecdr814gcDisableISRs\n");taskDelay(10); 00280 ecdr814gcDisableISRs(ecdr814Dev, UNI_VME_INT_DMA_DONE | 00281 UNI_VME_INT_LINT0 | 00282 UNI_VME_INT_LINT1 | 00283 UNI_VME_INT_LINT2 | 00284 UNI_VME_INT_LINT3 | 00285 UNI_VME_INT_LINT4 | 00286 UNI_VME_INT_LINT5 | 00287 UNI_VME_INT_LINT6 | 00288 UNI_VME_INT_LINT7); 00289 printf("enable flash\n");taskDelay(10); 00290 ecdr814Dev->hECDR814->CSR |= FLASH_SELECT_01 | ENABLE_FLASH_ADDRESS; 00291 printf("reflash\n");taskDelay(10); 00292 ecdr814gcReFlash((char *)((INT32 *)arg)[1], (long *)ecdr814Dev->hFPGA, 0, 38); 00293 printf("reconfigure\n");taskDelay(10); 00294 ecdr814Dev->hECDR814->CSR ^= FLASH_SELECT_01 | ENABLE_FLASH_ADDRESS | REGONFIGURE_FPGA; 00295 printf("enable ISRs\n");taskDelay(10); 00296 if((ecdr814Dev->notification & ECDR814_POLL_DATA) != ECDR814_POLL_DATA) 00297 ecdr814gcEnableISRs(ecdr814Dev, UNI_VME_INT_LINT0 | 00298 UNI_VME_INT_LINT1 | 00299 UNI_VME_INT_LINT2 | 00300 UNI_VME_INT_LINT3 | 00301 UNI_VME_INT_LINT4 | 00302 UNI_VME_INT_LINT5 | 00303 UNI_VME_INT_LINT6 | 00304 UNI_VME_INT_LINT7); 00305 if((ecdr814Dev->notification & ECDR814_POLL_DMA) != ECDR814_POLL_DMA) 00306 ecdr814gcEnableISRs(ecdr814Dev, UNI_VME_INT_DMA_DONE); 00307 break; 00308 case 1: 00309 printf("ecdr814gcDisableISRs\n");taskDelay(10); 00310 ecdr814gcDisableISRs(ecdr814Dev, UNI_VME_INT_DMA_DONE | 00311 UNI_VME_INT_LINT0 | 00312 UNI_VME_INT_LINT1 | 00313 UNI_VME_INT_LINT2 | 00314 UNI_VME_INT_LINT3 | 00315 UNI_VME_INT_LINT4 | 00316 UNI_VME_INT_LINT5 | 00317 UNI_VME_INT_LINT6 | 00318 UNI_VME_INT_LINT7); 00319 printf("enable flash\n");taskDelay(10); 00320 ecdr814Dev->hECDR814->CSR |= FLASH_SELECT_23 | ENABLE_FLASH_ADDRESS; 00321 printf("reflash\n");taskDelay(10); 00322 ecdr814gcReFlash((char *)((INT32 *)arg)[1], (long *)ecdr814Dev->hFPGA, 39, 70); 00323 printf("reconfigure\n");taskDelay(10); 00324 ecdr814Dev->hECDR814->CSR ^= FLASH_SELECT_23 | ENABLE_FLASH_ADDRESS | REGONFIGURE_FPGA; 00325 printf("enable ISRs\n");taskDelay(10); 00326 if((ecdr814Dev->notification & ECDR814_POLL_DATA) != ECDR814_POLL_DATA) 00327 ecdr814gcEnableISRs(ecdr814Dev, UNI_VME_INT_LINT0 | 00328 UNI_VME_INT_LINT1 | 00329 UNI_VME_INT_LINT2 | 00330 UNI_VME_INT_LINT3 | 00331 UNI_VME_INT_LINT4 | 00332 UNI_VME_INT_LINT5 | 00333 UNI_VME_INT_LINT6 | 00334 UNI_VME_INT_LINT7); 00335 if((ecdr814Dev->notification & ECDR814_POLL_DMA) != ECDR814_POLL_DMA) 00336 ecdr814gcEnableISRs(ecdr814Dev, UNI_VME_INT_DMA_DONE); 00337 break; 00338 case 2: 00339 printf("ecdr814gcDisableISRs\n");taskDelay(10); 00340 ecdr814gcDisableISRs(ecdr814Dev, UNI_VME_INT_DMA_DONE | 00341 UNI_VME_INT_LINT0 | 00342 UNI_VME_INT_LINT1 | 00343 UNI_VME_INT_LINT2 | 00344 UNI_VME_INT_LINT3 | 00345 UNI_VME_INT_LINT4 | 00346 UNI_VME_INT_LINT5 | 00347 UNI_VME_INT_LINT6 | 00348 UNI_VME_INT_LINT7); 00349 printf("enable flash\n");taskDelay(10); 00350 ecdr814Dev->hECDR814->CSR |= FLASH_SELECT_45 | ENABLE_FLASH_ADDRESS; 00351 printf("reflash\n");taskDelay(10); 00352 ecdr814gcReFlash((char *)((INT32 *)arg)[1], (long *)ecdr814Dev->hFPGA, 71, 102); 00353 printf("reconfigure\n");taskDelay(10); 00354 ecdr814Dev->hECDR814->CSR ^= FLASH_SELECT_45 | ENABLE_FLASH_ADDRESS | REGONFIGURE_FPGA; 00355 printf("enable ISRs\n");taskDelay(10); 00356 if((ecdr814Dev->notification & ECDR814_POLL_DATA) != ECDR814_POLL_DATA) 00357 ecdr814gcEnableISRs(ecdr814Dev, UNI_VME_INT_LINT0 | 00358 UNI_VME_INT_LINT1 | 00359 UNI_VME_INT_LINT2 | 00360 UNI_VME_INT_LINT3 | 00361 UNI_VME_INT_LINT4 | 00362 UNI_VME_INT_LINT5 | 00363 UNI_VME_INT_LINT6 | 00364 UNI_VME_INT_LINT7); 00365 if((ecdr814Dev->notification & ECDR814_POLL_DMA) != ECDR814_POLL_DMA) 00366 ecdr814gcEnableISRs(ecdr814Dev, UNI_VME_INT_DMA_DONE); 00367 break; 00368 case 3: 00369 printf("ecdr814gcDisableISRs\n");taskDelay(10); 00370 ecdr814gcDisableISRs(ecdr814Dev, UNI_VME_INT_DMA_DONE | 00371 UNI_VME_INT_LINT0 | 00372 UNI_VME_INT_LINT1 | 00373 UNI_VME_INT_LINT2 | 00374 UNI_VME_INT_LINT3 | 00375 UNI_VME_INT_LINT4 | 00376 UNI_VME_INT_LINT5 | 00377 UNI_VME_INT_LINT6 | 00378 UNI_VME_INT_LINT7); 00379 printf("enable flash\n");taskDelay(10); 00380 ecdr814Dev->hECDR814->CSR |= FLASH_SELECT_67 | ENABLE_FLASH_ADDRESS; 00381 printf("reflash\n");taskDelay(10); 00382 ecdr814gcReFlash((char *)((INT32 *)arg)[1], (long *)ecdr814Dev->hFPGA, 103, 134); 00383 printf("reconfigure\n");taskDelay(10); 00384 ecdr814Dev->hECDR814->CSR ^= FLASH_SELECT_67 | ENABLE_FLASH_ADDRESS | REGONFIGURE_FPGA; 00385 printf("enable ISRs\n");taskDelay(10); 00386 if((ecdr814Dev->notification & ECDR814_POLL_DATA) != ECDR814_POLL_DATA) 00387 ecdr814gcEnableISRs(ecdr814Dev, UNI_VME_INT_LINT0 | 00388 UNI_VME_INT_LINT1 | 00389 UNI_VME_INT_LINT2 | 00390 UNI_VME_INT_LINT3 | 00391 UNI_VME_INT_LINT4 | 00392 UNI_VME_INT_LINT5 | 00393 UNI_VME_INT_LINT6 | 00394 UNI_VME_INT_LINT7); 00395 if((ecdr814Dev->notification & ECDR814_POLL_DMA) != ECDR814_POLL_DMA) 00396 ecdr814gcEnableISRs(ecdr814Dev, UNI_VME_INT_DMA_DONE); 00397 break; 00398 } 00399 break; 00400 00401 case ECDR814_PROGRAM_PLLS: 00402 channel = arg; 00403 ecdr814gcProgramPlls(ecdr814Dev->hChannelPairHandle[channel / 2], 00404 &(ecdr814Dev->hSetup->channelPairInfo[channel / 2]), channel % 2); 00405 break; 00406 00407 case ECDR814_READ_INI_FILE: 00408 bzero((char *)ecdr814Dev->hSetup, sizeof(SETUP_t)); 00409 strcpy(ecdr814Dev->hSetup->iniFile, (char *)arg); 00410 return(ecdr814gcScanFile(ecdr814Dev->hSetup)); 00411 00412 case ECDR814_RELEASE: 00413 semGive(ecdr814Dev->releaseSem); 00414 semGive(ecdr814Dev->collection0DoneSem); 00415 semGive(ecdr814Dev->collection1DoneSem); 00416 semGive(ecdr814Dev->collection2DoneSem); 00417 semGive(ecdr814Dev->collection3DoneSem); 00418 semGive(ecdr814Dev->collection4DoneSem); 00419 semGive(ecdr814Dev->collection5DoneSem); 00420 semGive(ecdr814Dev->collection6DoneSem); 00421 semGive(ecdr814Dev->collection7DoneSem); 00422 break; 00423 00424 case ECDR814_RESET: 00425 UniverseII_Reset(ecdr814Dev->hUniverseII); 00426 taskDelay(10); 00427 ecdr814gcInstallISR(ecdr814Dev); 00428 break; 00429 00430 00431 case ECDR814_SELECT_NOTIFICATION: 00432 ecdr814Dev->notification = (INT32)arg; 00433 break; 00434 00435 case ECDR814_SET_BUFFER: 00436 channel = ((INT32 *)arg)[0]; 00437 subChannel = ((INT32 *)arg)[1]; 00438 ecdr814Dev->hSetup->buffers[channel][subChannel] = (INT32 *)((INT32 *)arg)[2]; 00439 break; 00440 00441 case ECDR814_SET_CHANNEL: 00442 ecdr814Dev->hSetup->channel = (INT32)arg; 00443 break; 00444 00445 case ECDR814_SET_NUM_TRIGS: 00446 ecdr814Dev->hECDR814->TCNT = (INT32)arg; 00447 break; 00448 00449 case ECDR814_SHOW: 00450 printf("\nCSR %08x\n", ecdr814Dev->hECDR814->CSR); 00451 printf("FLAGS %08x\n", ecdr814Dev->hECDR814->FLAGS); 00452 printf("INTMASK %08x\n", ecdr814Dev->hECDR814->INTMASK); 00453 printf("INTSRC %08x\n", ecdr814Dev->hECDR814->INTSRC); 00454 printf("HEAD0 %08x\n", ecdr814Dev->hECDR814->HEAD0); 00455 printf("HEAD1 %08x\n", ecdr814Dev->hECDR814->HEAD1); 00456 00457 for(i = 0; i < 4; i++) 00458 { 00459 printf("Hit a key to continue\n"); 00460 while(!Key_Hit()); 00461 if(i == 0) 00462 printf("\nReceiver pair 01\n"); 00463 else if(i == 1) 00464 printf("\nReceiver pair 23\n"); 00465 else if(i == 2) 00466 printf("\nReceiver pair 45\n"); 00467 else if(i == 3) 00468 printf("\nReceiver pair 67\n"); 00469 ecdr814gcReadbackGray(ecdr814Dev->hChannelPairHandle[i]); 00470 } 00471 break; 00472 00473 case ECDR814_SHOW_PROGRAM_INFO: 00474 printf("\nCSR %08x\n", 00475 ecdr814Dev->hSetup->ecdr814Info.CSR); 00476 printf("FLAGS %08x\n", 00477 ecdr814Dev->hSetup->ecdr814Info.FLAGS); 00478 printf("INTMASK %08x\n", 00479 ecdr814Dev->hSetup->ecdr814Info.INTMASK); 00480 printf("INTSRC %08x\n", 00481 ecdr814Dev->hSetup->ecdr814Info.INTSRC); 00482 printf("HEAD0 %08x\n", 00483 ecdr814Dev->hSetup->ecdr814Info.HEAD0); 00484 printf("HEAD1 %08x\n", 00485 ecdr814Dev->hSetup->ecdr814Info.HEAD1); 00486 00487 for(i = 0; i < 4; i++) 00488 { 00489 printf("Hit a key to continue\n"); 00490 while(!Key_Hit()); 00491 printf("\nCSR_C%d%d %08x\n", i * 2, (i * 2) + 1, 00492 ecdr814Dev->hSetup->channelPairInfo[i].CSR1); 00493 printf("DWS_C%d %08x\n", i * 2, 00494 ecdr814Dev->hSetup->channelPairInfo[i].DWS1); 00495 printf("CSR_C%d %08x\n", (i * 2) + 1, 00496 ecdr814Dev->hSetup->channelPairInfo[i].CSR2); 00497 printf("DWS_C%d %08x\n", (i * 2) + 1, 00498 ecdr814Dev->hSetup->channelPairInfo[i].DWS2); 00499 00500 for(k = 0; k < 2; k++) 00501 { 00502 for(l = 0; l < 4; l++) 00503 { 00504 printf("\nReceiver %d\n", (i * 2) + k); 00505 printf("Phase %08x\n", 00506 ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].Phase); 00507 printf("FreqHW %08x\n", 00508 ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].FreqHW); 00509 printf("FreqLW %08x\n", 00510 ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].FreqLW); 00511 printf("ChReset %08x\n", 00512 ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].ChReset); 00513 printf("FreqSync %08x\n", 00514 ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].FreqSync); 00515 printf("NCOSync %08x\n", 00516 ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].NCOSync); 00517 printf("ZPAD_Mode_Ctl %08x\n", 00518 ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].ZPAD_Mode_Ctl); 00519 printf("FlushSync %08x\n", 00520 ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].FlushSync); 00521 printf("DecRatio %08x\n", 00522 ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].DecRatio); 00523 printf("CIC_Scale %08x\n", 00524 ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].CIC_Scale); 00525 printf("SplitIQ %08x\n", 00526 ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].SplitIQ); 00527 printf("CFIR %08x\n", 00528 ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].CFIR); 00529 printf("PFIR %08x\n", 00530 ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].PFIR); 00531 printf("Input %08x\n", 00532 ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].Input); 00533 printf("PeakCtrl %08x\n", 00534 ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].PeakCtrl); 00535 printf("PeakCnt %08x\n", 00536 ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].PeakCnt); 00537 printf("FineGain %08x\n", 00538 ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].FineGain); 00539 } 00540 } 00541 } 00542 break; 00543 00544 case ECDR814_START: 00545 printf("ECDR814_START\n");taskDelay(10); 00546 trigs = ((INT32 *)arg)[0]; 00547 printf("trigs %d trigType %d\n", trigs, trigType);taskDelay(10); 00548 trigType = ((INT32 *)arg)[1]; 00549 printf("trigs %d trigType %d\n", trigs, trigType);taskDelay(10); 00550 if((ecdr814Dev->notification & ECDR814_POLL_DATA) == ECDR814_POLL_DATA) 00551 { 00552 printf("poll data\n"); 00553 ecdr814gcDisableISRs(ecdr814Dev, UNI_VME_INT_LINT0 | 00554 UNI_VME_INT_LINT1 | 00555 UNI_VME_INT_LINT2 | 00556 UNI_VME_INT_LINT3 | 00557 UNI_VME_INT_LINT4 | 00558 UNI_VME_INT_LINT5 | 00559 UNI_VME_INT_LINT6 | 00560 UNI_VME_INT_LINT7); 00561 } 00562 else 00563 ecdr814gcEnableISRs(ecdr814Dev, UNI_VME_INT_LINT0 | 00564 UNI_VME_INT_LINT1 | 00565 UNI_VME_INT_LINT2 | 00566 UNI_VME_INT_LINT3 | 00567 UNI_VME_INT_LINT4 | 00568 UNI_VME_INT_LINT5 | 00569 UNI_VME_INT_LINT6 | 00570 UNI_VME_INT_LINT7); 00571 00572 if((ecdr814Dev->notification & ECDR814_POLL_DMA) == ECDR814_POLL_DMA) 00573 { 00574 printf("poll dma\n"); 00575 ecdr814gcDisableISRs(ecdr814Dev, UNI_VME_INT_DMA_DONE); 00576 } 00577 else 00578 ecdr814gcEnableISRs(ecdr814Dev, UNI_VME_INT_DMA_DONE); 00579 00580 ecdr814Dev->hECDR814->INTMASK = (CHANNEL_0_INT_ENABLE | CHANNEL_1_INT_ENABLE | 00581 CHANNEL_2_INT_ENABLE | CHANNEL_3_INT_ENABLE | 00582 CHANNEL_4_INT_ENABLE | CHANNEL_5_INT_ENABLE | 00583 CHANNEL_6_INT_ENABLE | CHANNEL_7_INT_ENABLE); 00584 if(trigs > 1) 00585 { 00586 ecdr814Dev->hECDR814->TCNT = trigs; 00587 ecdr814Dev->hECDR814->INTSRC = (CHANNEL_0_TRIG_CNT_INT | CHANNEL_1_TRIG_CNT_INT | 00588 CHANNEL_2_TRIG_CNT_INT | CHANNEL_3_TRIG_CNT_INT | 00589 CHANNEL_4_TRIG_CNT_INT | CHANNEL_5_TRIG_CNT_INT | 00590 CHANNEL_6_TRIG_CNT_INT | CHANNEL_7_TRIG_CNT_INT); 00591 } 00592 else 00593 { 00594 ecdr814Dev->hECDR814->TCNT = 0; 00595 ecdr814Dev->hECDR814->INTSRC = (CHANNEL_0_DONE_INT | CHANNEL_1_DONE_INT | 00596 CHANNEL_2_DONE_INT | CHANNEL_3_DONE_INT | 00597 CHANNEL_4_DONE_INT | CHANNEL_5_DONE_INT | 00598 CHANNEL_6_DONE_INT | CHANNEL_7_DONE_INT); 00599 } 00600 00601 if(trigType == 0) 00602 { 00603 for(i = 0; i < (INT32)trigs; i++) 00604 ecdr814Dev->hECDR814->CSR = (CSR_MASK & ecdr814Dev->hSetup->ecdr814Info.CSR) | SW_SYNC_PULSE; 00605 } 00606 break; 00607 00608 case ECDR814_STOP: 00609 printf("ECDR814_STOP\n");taskDelay(1); 00610 for(i = 0; i < 4; i++) 00611 { 00612 ecdr814Dev->hChannelPairHandle[i]->CSR1 = (ecdr814Dev->hChannelPairHandle[i]->CSR1 & CHAN_CSR_MASK) | 00613 SRAM_POINTER_0_RESET | SRAM_POINTER_1_RESET | 00614 SRAM_POINTER_2_RESET | SRAM_POINTER_3_RESET | 00615 PLL_RESET_RELEASE; 00616 ecdr814Dev->hChannelPairHandle[i]->CSR2 = (ecdr814Dev->hChannelPairHandle[i]->CSR2 & CHAN_CSR_MASK) | 00617 SRAM_POINTER_0_RESET | SRAM_POINTER_1_RESET | 00618 SRAM_POINTER_2_RESET | SRAM_POINTER_3_RESET | 00619 PLL_RESET_RELEASE; 00620 } 00621 break; 00622 00623 case ECDR814_TEST_FLASH: 00624 for(i = 0; i < 36; i++) 00625 { 00626 ecdr814Dev->hECDR814->CSR |= FLASH_SELECT_01 | ENABLE_FLASH_ADDRESS; 00627 ecdr814gcTestFlash(pattern[i], (long *)ecdr814Dev->hFPGA, 0, 38); 00628 ecdr814Dev->hECDR814->CSR ^= FLASH_SELECT_01 | ENABLE_FLASH_ADDRESS; 00629 00630 ecdr814Dev->hECDR814->CSR |= FLASH_SELECT_23 | ENABLE_FLASH_ADDRESS; 00631 ecdr814gcTestFlash(pattern[i], (long *)ecdr814Dev->hFPGA, 39, 70); 00632 ecdr814Dev->hECDR814->CSR ^= FLASH_SELECT_23 | ENABLE_FLASH_ADDRESS; 00633 00634 ecdr814Dev->hECDR814->CSR |= FLASH_SELECT_45 | ENABLE_FLASH_ADDRESS; 00635 ecdr814gcTestFlash(pattern[i], (long *)ecdr814Dev->hFPGA, 71, 102); 00636 ecdr814Dev->hECDR814->CSR ^= FLASH_SELECT_45 | ENABLE_FLASH_ADDRESS; 00637 00638 ecdr814Dev->hECDR814->CSR |= FLASH_SELECT_67 | ENABLE_FLASH_ADDRESS; 00639 ecdr814gcTestFlash(pattern[i], (long *)ecdr814Dev->hFPGA, 103, 134); 00640 ecdr814Dev->hECDR814->CSR ^= FLASH_SELECT_67 | ENABLE_FLASH_ADDRESS; 00641 } 00642 break; 00643 00644 case ECDR814_TRIG: 00645 if((ecdr814Dev->hSetup->ecdr814Info.CSR & ENABLE_EXT_SYNC) != ENABLE_EXT_SYNC) 00646 ecdr814Dev->hECDR814->CSR |= SW_SYNC_PULSE; 00647 break; 00648 00649 case ECDR814_VERIFY_FLASH: 00650 pair = ((INT32 *)arg)[0]; 00651 switch(pair) 00652 { 00653 case 0: 00654 ecdr814Dev->hECDR814->CSR |= FLASH_SELECT_01 | ENABLE_FLASH_ADDRESS; 00655 ecdr814gcVerifyFlash((char *)((INT32 *)arg)[1], (long *)ecdr814Dev->hFPGA); 00656 ecdr814Dev->hECDR814->CSR ^= FLASH_SELECT_01 | ENABLE_FLASH_ADDRESS; 00657 break; 00658 case 1: 00659 ecdr814Dev->hECDR814->CSR |= FLASH_SELECT_23 | ENABLE_FLASH_ADDRESS; 00660 ecdr814gcVerifyFlash((char *)((INT32 *)arg)[1], (long *)ecdr814Dev->hFPGA); 00661 ecdr814Dev->hECDR814->CSR ^= FLASH_SELECT_23 | ENABLE_FLASH_ADDRESS; 00662 break; 00663 case 2: 00664 ecdr814Dev->hECDR814->CSR |= FLASH_SELECT_45 | ENABLE_FLASH_ADDRESS; 00665 ecdr814gcVerifyFlash((char *)((INT32 *)arg)[1], (long *)ecdr814Dev->hFPGA); 00666 ecdr814Dev->hECDR814->CSR ^= FLASH_SELECT_45 | ENABLE_FLASH_ADDRESS; 00667 break; 00668 case 3: 00669 ecdr814Dev->hECDR814->CSR |= FLASH_SELECT_67 | ENABLE_FLASH_ADDRESS; 00670 ecdr814gcVerifyFlash((char *)((INT32 *)arg)[1], (long *)ecdr814Dev->hFPGA); 00671 ecdr814Dev->hECDR814->CSR ^= FLASH_SELECT_67 | ENABLE_FLASH_ADDRESS; 00672 break; 00673 } 00674 00675 default: 00676 printf("\necdr81gcIoctl: Unknown Request Code...aborting\n"); 00677 return EC_ERROR; 00678 } 00679 return EC_OKAY; 00680 }
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