ecdr814gcIoctl.cpp

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//  (c) Copyright 2004 Echotek Corp.  All Rights Reserved

#include <vxWorks.h>
#include <vxLib.h>
#include "mv5500/config.h"
#include "vme.h"

#include "ecdr814gcDrv.h"

STATUS ecdr814gcIoctl(ECDR814_DEV_HANDLE ecdr814Dev, INT32 requestCode, INT32 arg)
{  
  DMA_TRANSFER_INFO_BLK DmaXfer[ECDR814_MAX_DMAS];
  INT32 i;
  INT32 channel;
  INT32 subChannel;
  INT32 pair;
  INT32 intStat;
  INT32 j;
  INT32 k;
  INT32 l;
  INT32 trigs;
  INT32 trigType;
  INT32 numChans;
  INT32 subChannelInfo[2];
  INT32 wordCount;
  INT32 useChan;
  INT32 pattern[36] = { 0x00000000, 0xFFFFFFFF, 0xAAAAAAAA, 0x55555555,
            0x00000001, 0x00000002, 0x00000004, 0x00000008,
            0x00000010, 0x00000020, 0x00000040, 0x00000080,
            0x00000100, 0x00000200, 0x00000400, 0x00000800,
            0x00001000, 0x00002000, 0x00004000, 0x00008000,
            0x00010000, 0x00020000, 0x00040000, 0x00080000,
            0x00100000, 0x00200000, 0x00400000, 0x00800000,
            0x01000000, 0x02000000, 0x04000000, 0x08000000,
            0x10000000, 0x20000000, 0x40000000, 0x80000000  };

  if(!ecdr814Dev->Is_Open)
  {
    printf("\necdr814gcIoctl: Device is not opened\n");
    return EC_ERROR;
  }
  switch(requestCode)
  {
    case ECDR814_CHECK:
    printf("ECDR814_CHECK\n");taskDelay(1);
     if(ecdr814Dev->notification == ECDR814_SEM_DATA)
     {
       semTake(ecdr814Dev->collection0DoneSem, WAIT_FOREVER);
       semTake(ecdr814Dev->collection1DoneSem, WAIT_FOREVER);
       semTake(ecdr814Dev->collection2DoneSem, WAIT_FOREVER);
       semTake(ecdr814Dev->collection3DoneSem, WAIT_FOREVER);
       semTake(ecdr814Dev->collection4DoneSem, WAIT_FOREVER);
       semTake(ecdr814Dev->collection5DoneSem, WAIT_FOREVER);
       semTake(ecdr814Dev->collection6DoneSem, WAIT_FOREVER);
       semTake(ecdr814Dev->collection7DoneSem, WAIT_FOREVER);
     }
     else
     {
       while((UINT32)ecdr814Dev->hUniverseII->VINT_STAT != (UINT32)0xFF000000)
        ;
       ecdr814Dev->hUniverseII->VINT_STAT = 0xFF000000;
     }
     break;

    case ECDR814_CLEAR:
     ecdr814Dev->hECDR814->CSR = (0x000001FF & ecdr814Dev->hSetup->ecdr814Info.CSR) & ~ENABLE_EXT_SYNC;

     ecdr814Dev->hChannelPairHandle[0]->CSR1 = (ecdr814Dev->hChannelPairHandle[0]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_0_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[0]->CSR1 = (ecdr814Dev->hChannelPairHandle[0]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_1_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[0]->CSR1 = (ecdr814Dev->hChannelPairHandle[0]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_2_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[0]->CSR1 = (ecdr814Dev->hChannelPairHandle[0]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_3_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[0]->CSR2 = (ecdr814Dev->hChannelPairHandle[0]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_0_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[0]->CSR2 = (ecdr814Dev->hChannelPairHandle[0]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_1_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[0]->CSR2 = (ecdr814Dev->hChannelPairHandle[0]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_2_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[0]->CSR2 = (ecdr814Dev->hChannelPairHandle[0]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_3_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[1]->CSR1 = (ecdr814Dev->hChannelPairHandle[1]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_0_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[1]->CSR1 = (ecdr814Dev->hChannelPairHandle[1]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_1_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[1]->CSR1 = (ecdr814Dev->hChannelPairHandle[1]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_2_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[1]->CSR1 = (ecdr814Dev->hChannelPairHandle[1]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_3_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[1]->CSR2 = (ecdr814Dev->hChannelPairHandle[1]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_0_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[1]->CSR2 = (ecdr814Dev->hChannelPairHandle[1]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_1_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[1]->CSR2 = (ecdr814Dev->hChannelPairHandle[1]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_2_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[1]->CSR2 = (ecdr814Dev->hChannelPairHandle[1]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_3_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[2]->CSR1 = (ecdr814Dev->hChannelPairHandle[2]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_0_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[2]->CSR1 = (ecdr814Dev->hChannelPairHandle[2]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_1_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[2]->CSR1 = (ecdr814Dev->hChannelPairHandle[2]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_2_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[2]->CSR1 = (ecdr814Dev->hChannelPairHandle[2]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_3_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[2]->CSR2 = (ecdr814Dev->hChannelPairHandle[2]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_0_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[2]->CSR2 = (ecdr814Dev->hChannelPairHandle[2]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_1_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[2]->CSR2 = (ecdr814Dev->hChannelPairHandle[2]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_2_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[2]->CSR2 = (ecdr814Dev->hChannelPairHandle[2]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_3_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[3]->CSR1 = (ecdr814Dev->hChannelPairHandle[3]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_0_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[3]->CSR1 = (ecdr814Dev->hChannelPairHandle[3]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_1_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[3]->CSR1 = (ecdr814Dev->hChannelPairHandle[3]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_2_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[3]->CSR1 = (ecdr814Dev->hChannelPairHandle[3]->CSR1 & CHAN_CSR_MASK) | SRAM_POINTER_3_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[3]->CSR2 = (ecdr814Dev->hChannelPairHandle[3]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_0_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[3]->CSR2 = (ecdr814Dev->hChannelPairHandle[3]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_1_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[3]->CSR2 = (ecdr814Dev->hChannelPairHandle[3]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_2_RESET | PLL_RESET_RELEASE;
     ecdr814Dev->hChannelPairHandle[3]->CSR2 = (ecdr814Dev->hChannelPairHandle[3]->CSR2 & CHAN_CSR_MASK) | SRAM_POINTER_3_RESET | PLL_RESET_RELEASE;
     EIEIO_SYNC;

     semTake(ecdr814Dev->collection0DoneSem, NO_WAIT);
     semTake(ecdr814Dev->collection1DoneSem, NO_WAIT);
     semTake(ecdr814Dev->collection2DoneSem, NO_WAIT);
     semTake(ecdr814Dev->collection3DoneSem, NO_WAIT);
     semTake(ecdr814Dev->collection4DoneSem, NO_WAIT);
     semTake(ecdr814Dev->collection5DoneSem, NO_WAIT);
     semTake(ecdr814Dev->collection6DoneSem, NO_WAIT);
     semTake(ecdr814Dev->collection7DoneSem, NO_WAIT);
     semTake(ecdr814Dev->transferDoneSem, NO_WAIT);
     semTake(ecdr814Dev->releaseSem, NO_WAIT);
     ecdr814Dev->Is_Busy=0;

     intStat = ecdr814Dev->hECDR814->INTSRC;
     break;

    case ECDR814_DISABLE:
     ecdr814Dev->hECDR814->CSR = (CSR_MASK & ecdr814Dev->hSetup->ecdr814Info.CSR) & ~ENABLE_EXT_SYNC;
     break;

    case ECDR814_DMA_CHAIN:
     for(i = 0; i < 8; i++)
     {
       subChannelInfo[0] = i;
       subChannelInfo[1] = (INT32)&numChans;
       ecdr814gcIoctl(ecdr814Dev, ECDR814_GET_NUM_SUB_CHANNELS, (int)subChannelInfo);
       if((i % 2) == 0)
       {     
         wordCount = (ecdr814Dev->hSetup->channelPairInfo[i / 2].DWS1 & 0x1FFFF) + 1;
       }
       else
       {
         wordCount = (ecdr814Dev->hSetup->channelPairInfo[i / 2].DWS2 & 0x1FFFF) + 1;
       }
       for(j = 0; j < numChans; j++)
       {
         useChan = j;
         if(numChans == 2)
          useChan = useChan * 2;
         if(ecdr814Dev->hSetup->transferType == SINGLE_READ_TRANSFER)
         {
           for(k = 0; k < (INT32)((wordCount * trigs) / numChans); k++)
           {
             ((UINT32 *)ecdr814Dev->hSetup->buffers[i][useChan])[k] = ((UINT32
             *)ecdr814Dev->mappedFifos[i][useChan])[k];
           }
         }
         else
         {
           DmaXfer[(i * numChans) + useChan].Mem_Addr       = (long)ecdr814Dev->hSetup->buffers[i][useChan];
           DmaXfer[(i * numChans) + useChan].Loc_Addr       = (long)ecdr814Dev->unmappedFifos[i][useChan];
           DmaXfer[(i * numChans) + useChan].Byte_Cnt       = (wordCount * 4 * trigs) / numChans;
           DmaXfer[(i * numChans) + useChan].Transfer_Type  = ecdr814Dev->hSetup->vmeDmaType;
           DmaXfer[(i * numChans) + useChan].Direction      = DMA_XFER_PCI_TO_VME;
           DmaXfer[(i * numChans) + useChan].DescriptorAddr = (long)(ecdr814Dev->hDmaDescriptors + ((i *
           numChans) + useChan) * 8);
         }
       }
     }
     if(ecdr814Dev->hSetup->transferType != SINGLE_READ_TRANSFER)
     {
       DMA_ChainTransfer((DMA_TRANSFER_INFO_BLK **)&DmaXfer, 8);  
       ecdr814Dev->hECDR814->LDCPP = DMA_DESC_OFFSET;  
       ecdr814Dev->hECDR814->LDGCS = DMA_START | DMA_CHAIN | DMA_INT_WHEN_DONE | DMA_INT_WHEN_LERR;
       DMA_TransferGo(ecdr814Dev->hUniverseII, DMA_DESC_OFFSET, DMA_START | DMA_CHAIN | DMA_INT_WHEN_DONE | DMA_INT_WHEN_LERR);
       if(ecdr814Dev->notification == ECDR814_SEM_DMA)
        semTake(ecdr814Dev->transferDoneSem, WAIT_FOREVER);
       else
       {
         while(ecdr814Dev->hUniverseII->VINT_STAT != DMA_DONE)
          ;
         ecdr814Dev->hUniverseII->VINT_STAT = DMA_DONE;
       }
     }
     break;
 
    case ECDR814_GET_BYTE_COUNT:
     channel = ((INT32 *)arg)[0];
     if((channel % 2) == 0)
     {     
       *(INT32 *)((INT32 *)arg)[1] = ((ecdr814Dev->hSetup->channelPairInfo[channel / 2].DWS1 & 0x1FFFF) + 1) * 4;
     }
     else
     {
       *(INT32 *)((INT32 *)arg)[1] = ((ecdr814Dev->hSetup->channelPairInfo[channel / 2].DWS2 & 0x1FFFF) + 1) * 4;
     }
     break;
      
    case ECDR814_GET_CHANNEL:
     *(INT32 *)arg = ecdr814Dev->hSetup->channel;
     break;
      
    case ECDR814_GET_DATA_MODE:
     if((ecdr814Dev->hSetup->channel % 2) == 0)
      *(INT32 *)arg = ecdr814Dev->hSetup->channelPairInfo[ecdr814Dev->hSetup->channel / 2].CSR1 & UNPACKED_DATA;
     else
      *(INT32 *)arg = ecdr814Dev->hSetup->channelPairInfo[ecdr814Dev->hSetup->channel / 2].CSR2 & UNPACKED_DATA;
     break;

    case ECDR814_GET_NUM_BITS:
     channel = ((INT32 *)arg)[0];
     if((channel % 2) == 0)
     {
        if((ecdr814Dev->hSetup->channelPairInfo[channel / 2].DATA_SEL1 & PACK_8_BIT) == PACK_8_BIT)
         *(INT32 *)((INT32 *)arg)[1] = EIGHT_BIT;
        else
         *(INT32 *)((INT32 *)arg)[1] = SIXTEEN_BIT;
     }
     else
     {
        if((ecdr814Dev->hSetup->channelPairInfo[channel / 2].DATA_SEL2 & PACK_8_BIT) == PACK_8_BIT) 
         *(INT32 *)((INT32 *)arg)[1] = EIGHT_BIT;
        else
         *(INT32 *)((INT32 *)arg)[1] = SIXTEEN_BIT;
     }
     break;

    case ECDR814_GET_NUM_SUB_CHANNELS:
     channel = ((INT32 *)arg)[0];
     if((channel % 2) == 0)
     {
       if((ecdr814Dev->hChannelPairHandle[channel / 2]->CSR1 & GC_4_CHAN) == GC_4_CHAN)
        *(INT32 *)((INT32 *)arg)[1] = FOUR_CHANNELS;
       else if((ecdr814Dev->hChannelPairHandle[channel / 2]->CSR1 & GC_2_CHAN) == GC_2_CHAN)
        *(INT32 *)((INT32 *)arg)[1] = TWO_CHANNELS;
       else
        *(INT32 *)((INT32 *)arg)[1] = ONE_CHANNEL;
     }
     else
     {
       if((ecdr814Dev->hChannelPairHandle[channel / 2]->CSR2 & GC_4_CHAN) == GC_4_CHAN)
        *(INT32 *)((INT32 *)arg)[1] = FOUR_CHANNELS;
       else if((ecdr814Dev->hChannelPairHandle[channel / 2]->CSR2 & GC_2_CHAN) == GC_2_CHAN)
        *(INT32 *)((INT32 *)arg)[1] = TWO_CHANNELS;
       else
        *(INT32 *)((INT32 *)arg)[1] = ONE_CHANNEL;
     }
     break;

    case ECDR814_GET_TRANSFER_TYPE:      
     *(INT32 *)arg = ecdr814Dev->hSetup->transferType;
     break;
      
    case ECDR814_HEADER_TEST:
     printf("Hit a key to trigger\n");
     while(!Key_Hit());
     ecdr814Dev->hECDR814->CSR = (CSR_MASK & ecdr814Dev->hSetup->ecdr814Info.CSR) | SW_SYNC_PULSE; 
     printf("HEAD0 REGISTER %08x\n", ecdr814Dev->hECDR814->HEAD0);
     printf("HEAD1 REGISTER %08x\n", ecdr814Dev->hECDR814->HEAD1);
     printf("HEAD0 SRAM %08x\n", *(int *)ecdr814Dev->hFIFOH0);
     printf("HEAD1 SRAM %08x\n", *(int *)ecdr814Dev->hFIFOH1);
     break;

    case ECDR814_MODIFY_WORD_COUNT:
     ecdr814Dev->hSetup->wordCount = (INT32)arg;
     break;      
       
    case ECDR814_PROGRAM_ALL_CHANNELS:    
//   ecdr814Dev->hECDR814->CSR = ecdr814Dev->hSetup->ecdr814Info.CSR;
     ecdr814Dev->hECDR814->CSR = ecdr814Dev->hSetup->ecdr814Info.CSR & ~ENABLE_EXT_SYNC;   // DHZ disable external trigger
     taskDelay(1);      
     for(i = 0; i < 4; i++)
      ecdr814gcProgramGray(ecdr814Dev->hChannelPairHandle[i], &(ecdr814Dev->hSetup->channelPairInfo[i]), 2);
     break;
      
    case ECDR814_PROGRAM_CHANNEL:
     channel = arg;
//   ecdr814Dev->hECDR814->CSR = ecdr814Dev->hSetup->ecdr814Info.CSR;
     ecdr814Dev->hECDR814->CSR = ecdr814Dev->hSetup->ecdr814Info.CSR & ~ENABLE_EXT_SYNC;   // DHZ disable external trigger
     taskDelay(1);
     ecdr814gcProgramGray(ecdr814Dev->hChannelPairHandle[channel / 2], &(ecdr814Dev->hSetup->channelPairInfo[channel / 2]), channel % 2);
     break;      
      
    case ECDR814_PROGRAM_FLASH:
     pair = ((INT32 *)arg)[0];
     switch(pair)
     {
       case 0:
printf("ecdr814gcDisableISRs\n");taskDelay(10);       
        ecdr814gcDisableISRs(ecdr814Dev, UNI_VME_INT_DMA_DONE | 
                                         UNI_VME_INT_LINT0 |
                                         UNI_VME_INT_LINT1 |
                                         UNI_VME_INT_LINT2 |
                                         UNI_VME_INT_LINT3 |
                                         UNI_VME_INT_LINT4 |
                                         UNI_VME_INT_LINT5 |
                                         UNI_VME_INT_LINT6 |
                                         UNI_VME_INT_LINT7);
printf("enable flash\n");taskDelay(10);       
        ecdr814Dev->hECDR814->CSR |= FLASH_SELECT_01 | ENABLE_FLASH_ADDRESS;
printf("reflash\n");taskDelay(10);        
        ecdr814gcReFlash((char *)((INT32 *)arg)[1], (long *)ecdr814Dev->hFPGA, 0, 38);
printf("reconfigure\n");taskDelay(10);        
        ecdr814Dev->hECDR814->CSR ^= FLASH_SELECT_01 | ENABLE_FLASH_ADDRESS | REGONFIGURE_FPGA;
printf("enable ISRs\n");taskDelay(10);        
        if((ecdr814Dev->notification & ECDR814_POLL_DATA) != ECDR814_POLL_DATA)
         ecdr814gcEnableISRs(ecdr814Dev, UNI_VME_INT_LINT0 |
                                         UNI_VME_INT_LINT1 |
                                         UNI_VME_INT_LINT2 |
                                         UNI_VME_INT_LINT3 |
                                         UNI_VME_INT_LINT4 |
                                         UNI_VME_INT_LINT5 |
                                         UNI_VME_INT_LINT6 |
                                         UNI_VME_INT_LINT7);
        if((ecdr814Dev->notification & ECDR814_POLL_DMA) != ECDR814_POLL_DMA)
         ecdr814gcEnableISRs(ecdr814Dev, UNI_VME_INT_DMA_DONE);
        break;
      case 1:
printf("ecdr814gcDisableISRs\n");taskDelay(10);       
        ecdr814gcDisableISRs(ecdr814Dev, UNI_VME_INT_DMA_DONE | 
                                         UNI_VME_INT_LINT0 |
                                         UNI_VME_INT_LINT1 |
                                         UNI_VME_INT_LINT2 |
                                         UNI_VME_INT_LINT3 |
                                         UNI_VME_INT_LINT4 |
                                         UNI_VME_INT_LINT5 |
                                         UNI_VME_INT_LINT6 |
                                         UNI_VME_INT_LINT7);
printf("enable flash\n");taskDelay(10);       
        ecdr814Dev->hECDR814->CSR |= FLASH_SELECT_23 | ENABLE_FLASH_ADDRESS;
printf("reflash\n");taskDelay(10);        
        ecdr814gcReFlash((char *)((INT32 *)arg)[1], (long *)ecdr814Dev->hFPGA, 39, 70);
printf("reconfigure\n");taskDelay(10);        
        ecdr814Dev->hECDR814->CSR ^= FLASH_SELECT_23 | ENABLE_FLASH_ADDRESS | REGONFIGURE_FPGA;
printf("enable ISRs\n");taskDelay(10);        
        if((ecdr814Dev->notification & ECDR814_POLL_DATA) != ECDR814_POLL_DATA)
         ecdr814gcEnableISRs(ecdr814Dev, UNI_VME_INT_LINT0 |
                                         UNI_VME_INT_LINT1 |
                                         UNI_VME_INT_LINT2 |
                                         UNI_VME_INT_LINT3 |
                                         UNI_VME_INT_LINT4 |
                                         UNI_VME_INT_LINT5 |
                                         UNI_VME_INT_LINT6 |
                                         UNI_VME_INT_LINT7);
        if((ecdr814Dev->notification & ECDR814_POLL_DMA) != ECDR814_POLL_DMA)
         ecdr814gcEnableISRs(ecdr814Dev, UNI_VME_INT_DMA_DONE);
        break;      
      case 2:
printf("ecdr814gcDisableISRs\n");taskDelay(10);       
        ecdr814gcDisableISRs(ecdr814Dev, UNI_VME_INT_DMA_DONE | 
                                         UNI_VME_INT_LINT0 |
                                         UNI_VME_INT_LINT1 |
                                         UNI_VME_INT_LINT2 |
                                         UNI_VME_INT_LINT3 |
                                         UNI_VME_INT_LINT4 |
                                         UNI_VME_INT_LINT5 |
                                         UNI_VME_INT_LINT6 |
                                         UNI_VME_INT_LINT7);
printf("enable flash\n");taskDelay(10);       
        ecdr814Dev->hECDR814->CSR |= FLASH_SELECT_45 | ENABLE_FLASH_ADDRESS;
printf("reflash\n");taskDelay(10);        
        ecdr814gcReFlash((char *)((INT32 *)arg)[1], (long *)ecdr814Dev->hFPGA, 71, 102);
printf("reconfigure\n");taskDelay(10);        
        ecdr814Dev->hECDR814->CSR ^= FLASH_SELECT_45 | ENABLE_FLASH_ADDRESS | REGONFIGURE_FPGA;
printf("enable ISRs\n");taskDelay(10);        
        if((ecdr814Dev->notification & ECDR814_POLL_DATA) != ECDR814_POLL_DATA)
         ecdr814gcEnableISRs(ecdr814Dev, UNI_VME_INT_LINT0 |
                                         UNI_VME_INT_LINT1 |
                                         UNI_VME_INT_LINT2 |
                                         UNI_VME_INT_LINT3 |
                                         UNI_VME_INT_LINT4 |
                                         UNI_VME_INT_LINT5 |
                                         UNI_VME_INT_LINT6 |
                                         UNI_VME_INT_LINT7);
        if((ecdr814Dev->notification & ECDR814_POLL_DMA) != ECDR814_POLL_DMA)
         ecdr814gcEnableISRs(ecdr814Dev, UNI_VME_INT_DMA_DONE);
        break;
      case 3:
printf("ecdr814gcDisableISRs\n");taskDelay(10);       
        ecdr814gcDisableISRs(ecdr814Dev, UNI_VME_INT_DMA_DONE | 
                                         UNI_VME_INT_LINT0 |
                                         UNI_VME_INT_LINT1 |
                                         UNI_VME_INT_LINT2 |
                                         UNI_VME_INT_LINT3 |
                                         UNI_VME_INT_LINT4 |
                                         UNI_VME_INT_LINT5 |
                                         UNI_VME_INT_LINT6 |
                                         UNI_VME_INT_LINT7);
printf("enable flash\n");taskDelay(10);       
        ecdr814Dev->hECDR814->CSR |= FLASH_SELECT_67 | ENABLE_FLASH_ADDRESS;
printf("reflash\n");taskDelay(10);        
        ecdr814gcReFlash((char *)((INT32 *)arg)[1], (long *)ecdr814Dev->hFPGA, 103, 134);
printf("reconfigure\n");taskDelay(10);        
        ecdr814Dev->hECDR814->CSR ^= FLASH_SELECT_67 | ENABLE_FLASH_ADDRESS | REGONFIGURE_FPGA;
printf("enable ISRs\n");taskDelay(10);        
        if((ecdr814Dev->notification & ECDR814_POLL_DATA) != ECDR814_POLL_DATA)
         ecdr814gcEnableISRs(ecdr814Dev, UNI_VME_INT_LINT0 |
                                         UNI_VME_INT_LINT1 |
                                         UNI_VME_INT_LINT2 |
                                         UNI_VME_INT_LINT3 |
                                         UNI_VME_INT_LINT4 |
                                         UNI_VME_INT_LINT5 |
                                         UNI_VME_INT_LINT6 |
                                         UNI_VME_INT_LINT7);
        if((ecdr814Dev->notification & ECDR814_POLL_DMA) != ECDR814_POLL_DMA)
         ecdr814gcEnableISRs(ecdr814Dev, UNI_VME_INT_DMA_DONE);
        break;
     }
     break;
      
    case ECDR814_PROGRAM_PLLS:
     channel = arg;
     ecdr814gcProgramPlls(ecdr814Dev->hChannelPairHandle[channel / 2],
     &(ecdr814Dev->hSetup->channelPairInfo[channel / 2]), channel % 2);
     break;      
     
    case ECDR814_READ_INI_FILE:
     bzero((char *)ecdr814Dev->hSetup, sizeof(SETUP_t));
     strcpy(ecdr814Dev->hSetup->iniFile, (char *)arg);
     return(ecdr814gcScanFile(ecdr814Dev->hSetup));
      
    case ECDR814_RELEASE:
     semGive(ecdr814Dev->releaseSem);
     semGive(ecdr814Dev->collection0DoneSem);
     semGive(ecdr814Dev->collection1DoneSem);
     semGive(ecdr814Dev->collection2DoneSem);
     semGive(ecdr814Dev->collection3DoneSem);
     semGive(ecdr814Dev->collection4DoneSem);
     semGive(ecdr814Dev->collection5DoneSem);
     semGive(ecdr814Dev->collection6DoneSem);
     semGive(ecdr814Dev->collection7DoneSem);
     break;

    case ECDR814_RESET:
      UniverseII_Reset(ecdr814Dev->hUniverseII);
      taskDelay(10);
      ecdr814gcInstallISR(ecdr814Dev);
     break;


    case ECDR814_SELECT_NOTIFICATION:
      ecdr814Dev->notification = (INT32)arg;
     break;

    case ECDR814_SET_BUFFER:
     channel = ((INT32 *)arg)[0];
     subChannel = ((INT32 *)arg)[1];
     ecdr814Dev->hSetup->buffers[channel][subChannel] = (INT32 *)((INT32 *)arg)[2];
     break;
      
    case ECDR814_SET_CHANNEL:
     ecdr814Dev->hSetup->channel = (INT32)arg;
     break;
      
    case ECDR814_SET_NUM_TRIGS:
     ecdr814Dev->hECDR814->TCNT = (INT32)arg;
     break;

    case ECDR814_SHOW:
     printf("\nCSR     %08x\n", ecdr814Dev->hECDR814->CSR);
     printf("FLAGS   %08x\n", ecdr814Dev->hECDR814->FLAGS);
     printf("INTMASK %08x\n", ecdr814Dev->hECDR814->INTMASK);
     printf("INTSRC %08x\n", ecdr814Dev->hECDR814->INTSRC);
     printf("HEAD0   %08x\n", ecdr814Dev->hECDR814->HEAD0);
     printf("HEAD1   %08x\n", ecdr814Dev->hECDR814->HEAD1);

     for(i = 0; i < 4; i++)
     {
       printf("Hit a key to continue\n");
       while(!Key_Hit());
       if(i == 0)
        printf("\nReceiver pair 01\n");
       else if(i == 1)
        printf("\nReceiver pair 23\n");
       else if(i == 2)
        printf("\nReceiver pair 45\n");
       else if(i == 3)
        printf("\nReceiver pair 67\n");
       ecdr814gcReadbackGray(ecdr814Dev->hChannelPairHandle[i]);
     }
     break;
      
    case ECDR814_SHOW_PROGRAM_INFO:
     printf("\nCSR     %08x\n",
     ecdr814Dev->hSetup->ecdr814Info.CSR);
     printf("FLAGS   %08x\n",
     ecdr814Dev->hSetup->ecdr814Info.FLAGS);
     printf("INTMASK %08x\n",
     ecdr814Dev->hSetup->ecdr814Info.INTMASK);
     printf("INTSRC %08x\n",
     ecdr814Dev->hSetup->ecdr814Info.INTSRC);
     printf("HEAD0   %08x\n",
     ecdr814Dev->hSetup->ecdr814Info.HEAD0);
     printf("HEAD1   %08x\n",
     ecdr814Dev->hSetup->ecdr814Info.HEAD1);

     for(i = 0; i < 4; i++)
     {
       printf("Hit a key to continue\n");
       while(!Key_Hit());
       printf("\nCSR_C%d%d   %08x\n", i * 2, (i * 2) + 1,
       ecdr814Dev->hSetup->channelPairInfo[i].CSR1);
       printf("DWS_C%d    %08x\n", i * 2,
       ecdr814Dev->hSetup->channelPairInfo[i].DWS1);
       printf("CSR_C%d    %08x\n", (i * 2) + 1,
       ecdr814Dev->hSetup->channelPairInfo[i].CSR2);
       printf("DWS_C%d    %08x\n", (i * 2) + 1,
       ecdr814Dev->hSetup->channelPairInfo[i].DWS2);        
        
       for(k = 0; k < 2; k++)
       {
         for(l = 0; l < 4; l++)
         {
           printf("\nReceiver %d\n", (i * 2) + k);
           printf("Phase          %08x\n",
           ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].Phase);
           printf("FreqHW         %08x\n",
           ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].FreqHW);
           printf("FreqLW         %08x\n",
           ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].FreqLW);
           printf("ChReset        %08x\n",
           ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].ChReset);
           printf("FreqSync       %08x\n",
           ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].FreqSync);
           printf("NCOSync        %08x\n",
           ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].NCOSync);
           printf("ZPAD_Mode_Ctl  %08x\n",
           ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].ZPAD_Mode_Ctl);
           printf("FlushSync      %08x\n",
           ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].FlushSync);
           printf("DecRatio       %08x\n",
           ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].DecRatio);
           printf("CIC_Scale      %08x\n",
           ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].CIC_Scale);
           printf("SplitIQ        %08x\n",
           ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].SplitIQ);
           printf("CFIR           %08x\n",
           ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].CFIR);
           printf("PFIR           %08x\n",
           ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].PFIR);
           printf("Input          %08x\n",
           ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].Input);
           printf("PeakCtrl       %08x\n",
           ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].PeakCtrl);
           printf("PeakCnt        %08x\n",
           ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].PeakCnt);
           printf("FineGain       %08x\n",
           ecdr814Dev->hSetup->channelPairInfo[i].channelInfo[k].gcChannelInfo[l].FineGain);
     }
       }
     }
     break;
      
    case ECDR814_START:
    printf("ECDR814_START\n");taskDelay(10);
      trigs = ((INT32 *)arg)[0];
printf("trigs %d trigType %d\n", trigs, trigType);taskDelay(10);      
      trigType = ((INT32 *)arg)[1];
printf("trigs %d trigType %d\n", trigs, trigType);taskDelay(10);      
      if((ecdr814Dev->notification & ECDR814_POLL_DATA) == ECDR814_POLL_DATA)
      {
    printf("poll data\n");  
        ecdr814gcDisableISRs(ecdr814Dev, UNI_VME_INT_LINT0 |
                                         UNI_VME_INT_LINT1 |
                                         UNI_VME_INT_LINT2 |
                                         UNI_VME_INT_LINT3 |
                                         UNI_VME_INT_LINT4 |
                                         UNI_VME_INT_LINT5 |
                                         UNI_VME_INT_LINT6 |
                                         UNI_VME_INT_LINT7);
      }
      else
        ecdr814gcEnableISRs(ecdr814Dev, UNI_VME_INT_LINT0 |
                                        UNI_VME_INT_LINT1 |
                                        UNI_VME_INT_LINT2 |
                                        UNI_VME_INT_LINT3 |
                                        UNI_VME_INT_LINT4 |
                                        UNI_VME_INT_LINT5 |
                                        UNI_VME_INT_LINT6 |
                                        UNI_VME_INT_LINT7);

      if((ecdr814Dev->notification & ECDR814_POLL_DMA) == ECDR814_POLL_DMA)
    {
    printf("poll dma\n");  
       ecdr814gcDisableISRs(ecdr814Dev, UNI_VME_INT_DMA_DONE);
    }
      else
       ecdr814gcEnableISRs(ecdr814Dev, UNI_VME_INT_DMA_DONE);

      ecdr814Dev->hECDR814->INTMASK = (CHANNEL_0_INT_ENABLE | CHANNEL_1_INT_ENABLE |
                                   CHANNEL_2_INT_ENABLE | CHANNEL_3_INT_ENABLE |
                                   CHANNEL_4_INT_ENABLE | CHANNEL_5_INT_ENABLE |
                                   CHANNEL_6_INT_ENABLE | CHANNEL_7_INT_ENABLE);
      if(trigs > 1)
      {
        ecdr814Dev->hECDR814->TCNT = trigs;
        ecdr814Dev->hECDR814->INTSRC = (CHANNEL_0_TRIG_CNT_INT | CHANNEL_1_TRIG_CNT_INT |
                                        CHANNEL_2_TRIG_CNT_INT | CHANNEL_3_TRIG_CNT_INT |
                                    CHANNEL_4_TRIG_CNT_INT | CHANNEL_5_TRIG_CNT_INT |
                                    CHANNEL_6_TRIG_CNT_INT | CHANNEL_7_TRIG_CNT_INT);
      }
      else
      {
        ecdr814Dev->hECDR814->TCNT = 0;
        ecdr814Dev->hECDR814->INTSRC = (CHANNEL_0_DONE_INT | CHANNEL_1_DONE_INT |
                                        CHANNEL_2_DONE_INT | CHANNEL_3_DONE_INT |
                                    CHANNEL_4_DONE_INT | CHANNEL_5_DONE_INT |
                                    CHANNEL_6_DONE_INT | CHANNEL_7_DONE_INT);
      }

      if(trigType == 0)
      {  
        for(i = 0; i < (INT32)trigs; i++)
         ecdr814Dev->hECDR814->CSR = (CSR_MASK & ecdr814Dev->hSetup->ecdr814Info.CSR) | SW_SYNC_PULSE; 
      }
     break;
     
    case ECDR814_STOP:
    printf("ECDR814_STOP\n");taskDelay(1);
      for(i = 0; i < 4; i++)
      {
        ecdr814Dev->hChannelPairHandle[i]->CSR1 = (ecdr814Dev->hChannelPairHandle[i]->CSR1 & CHAN_CSR_MASK) | 
                              SRAM_POINTER_0_RESET | SRAM_POINTER_1_RESET | 
                              SRAM_POINTER_2_RESET | SRAM_POINTER_3_RESET |
                                                  PLL_RESET_RELEASE;
        ecdr814Dev->hChannelPairHandle[i]->CSR2 = (ecdr814Dev->hChannelPairHandle[i]->CSR2 & CHAN_CSR_MASK) | 
                              SRAM_POINTER_0_RESET | SRAM_POINTER_1_RESET | 
                              SRAM_POINTER_2_RESET | SRAM_POINTER_3_RESET |
                                                  PLL_RESET_RELEASE;
      }
     break;

    case ECDR814_TEST_FLASH:
      for(i = 0; i < 36; i++)
      {
        ecdr814Dev->hECDR814->CSR |= FLASH_SELECT_01 | ENABLE_FLASH_ADDRESS;
        ecdr814gcTestFlash(pattern[i], (long *)ecdr814Dev->hFPGA, 0, 38);
        ecdr814Dev->hECDR814->CSR ^= FLASH_SELECT_01 | ENABLE_FLASH_ADDRESS;

        ecdr814Dev->hECDR814->CSR |= FLASH_SELECT_23 | ENABLE_FLASH_ADDRESS;
        ecdr814gcTestFlash(pattern[i], (long *)ecdr814Dev->hFPGA, 39, 70);
        ecdr814Dev->hECDR814->CSR ^= FLASH_SELECT_23 | ENABLE_FLASH_ADDRESS;

        ecdr814Dev->hECDR814->CSR |= FLASH_SELECT_45 | ENABLE_FLASH_ADDRESS;
        ecdr814gcTestFlash(pattern[i], (long *)ecdr814Dev->hFPGA, 71, 102);
        ecdr814Dev->hECDR814->CSR ^= FLASH_SELECT_45 | ENABLE_FLASH_ADDRESS;

        ecdr814Dev->hECDR814->CSR |= FLASH_SELECT_67 | ENABLE_FLASH_ADDRESS;
        ecdr814gcTestFlash(pattern[i], (long *)ecdr814Dev->hFPGA, 103, 134);
        ecdr814Dev->hECDR814->CSR ^= FLASH_SELECT_67 | ENABLE_FLASH_ADDRESS;
      }
      break;

    case ECDR814_TRIG:
     if((ecdr814Dev->hSetup->ecdr814Info.CSR & ENABLE_EXT_SYNC) != ENABLE_EXT_SYNC)
       ecdr814Dev->hECDR814->CSR |= SW_SYNC_PULSE;
     break;

    case ECDR814_VERIFY_FLASH:
      pair = ((INT32 *)arg)[0];
      switch(pair)
      {
        case 0:
          ecdr814Dev->hECDR814->CSR |= FLASH_SELECT_01 | ENABLE_FLASH_ADDRESS;
          ecdr814gcVerifyFlash((char *)((INT32 *)arg)[1], (long *)ecdr814Dev->hFPGA);
          ecdr814Dev->hECDR814->CSR ^= FLASH_SELECT_01 | ENABLE_FLASH_ADDRESS;
          break;
        case 1:
          ecdr814Dev->hECDR814->CSR |= FLASH_SELECT_23 | ENABLE_FLASH_ADDRESS;
          ecdr814gcVerifyFlash((char *)((INT32 *)arg)[1], (long *)ecdr814Dev->hFPGA);
          ecdr814Dev->hECDR814->CSR ^= FLASH_SELECT_23 | ENABLE_FLASH_ADDRESS;
          break;      
        case 2:
          ecdr814Dev->hECDR814->CSR |= FLASH_SELECT_45 | ENABLE_FLASH_ADDRESS;
          ecdr814gcVerifyFlash((char *)((INT32 *)arg)[1], (long *)ecdr814Dev->hFPGA);
          ecdr814Dev->hECDR814->CSR ^= FLASH_SELECT_45 | ENABLE_FLASH_ADDRESS;
          break;      
        case 3:
          ecdr814Dev->hECDR814->CSR |= FLASH_SELECT_67 | ENABLE_FLASH_ADDRESS;
          ecdr814gcVerifyFlash((char *)((INT32 *)arg)[1], (long *)ecdr814Dev->hFPGA);
          ecdr814Dev->hECDR814->CSR ^= FLASH_SELECT_67 | ENABLE_FLASH_ADDRESS;
          break;
      }  

    default: 
     printf("\necdr81gcIoctl: Unknown Request Code...aborting\n");
     return EC_ERROR;
  }
  return EC_OKAY;
}

---