| US 7,346,872 B2 | ||
| Functional timing analysis for characterization of virtual component blocks | ||
| Hakan Yalcin, San Jose, Calif. (US); Robert J. Palmero, Shoreview, Minn. (US); Karem A. Sakallah, Ann Arbor, Mich. (US); Mohammad S. Mortazavi, Santa Clara, Calif. (US); and Cyrus Bamji, Fremont, Calif. (US) | ||
| Assigned to Cadence Design Systems, Inc., San Jose, Calif. (US) | ||
| Filed on Sep. 24, 2002, as Appl. No. 10/255,119. | ||
| Application 10/255119 is a continuation of application No. 09/477710, filed on Dec. 28, 1999, granted, now 6,457,159. | ||
| Claims priority of provisional application 60/114253, filed on Dec. 29, 1998. | ||
| Prior Publication US 2003/0140324 A1, Jul. 24, 2003 | ||
| Int. Cl. G06F 9/45 (2006.01); G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—6 | 19 Claims |
| 1. A method of merging a set of delay tables, each of said delay tables comprising as elements a plurality of delay values,
said method comprising the steps of:
merging into a new delay table a group of delay tables whose elements fall within a specified tolerance of the elements in
similar relative positions of all other delay tables within the group, wherein said delay tables are merged based on a closeness
with respect to the specified tolerance;
selecting as elements for the new delay table a maximum of all the elements in similar relative positions of all the delay
tables in the group;
calculating, individually for each delay table, an aggregate sum of all of the elements in the delay table; and
selecting a set of closeness candidates for a given delay table based upon said specified tolerance and a size of said given
delay table, said set of closeness candidates including said group of delay tables.
|