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To: "'Hubert van Hecke'" 
From: Mike Emery 
Subject: Re: ramp, and dacs
Status: RO

Hubert,
Check out the 1997 NSS paper about the amuadc for more details.

The ramp slews negative starting from the Vref voltage and bottoming out at
approximately 0V (gnd) plus a little saturation voltage (50 - 100 mV or so).
The slew rate is controlled by the Iref DAC, which sets the current used for
charging a capacitor (on-chip) to create the ramp.  The larger the current
the steeper the slope.  The capacitor is reset when CLOCK_ENABLE returns
low, which happens after Full Scale Count (FSC) occurs.

The Vcorr DAC is not involved in the ramp.  It is used as a reference
voltage in the AMU correlator circuit.  Sort of a "pseudo-ground".

Mike


At 08:15 AM 6/4/98 -0600, you wrote:
>Hi Mike, 
>I recall that when we were there, we looked at the ramp voltage, and changed 
>the picture by setting various voltages. I don't have a deep understanding of 
>what all these dac settings do. Could you maybe fax me a sketch of the ramp 
>and which dac voltage affects the width, slope etc.     thanks, Hubert
>--
>---------------------------------------------------------------------
>--- Hubert van Hecke             ---      Los Alamos National Lab ---
>--- group P-25                   ---      phone: (505) 667 5384   ---
>--- email: hubert@lanl.gov       ---      fax  : (505) 665 7920   ---
>--- www home page: http://p2hp2.lanl.gov/people/hubert/home.html  ---
>---------------------------------------------------------------------
>a sketck 
>
Michael S. Emery
						
423-574-5654 	(Office)				
423-576-2813 	(FAX)					
www.ic.ornl.gov/rd-groups/msd/	(Web site)		

Monolithic Systems Development Group
Instrumentation & Controls Division
Oak Ridge National Laboratory

Mail:
ORNL
Bldg 3500  MS-6006
Oak Ridge, TN 37831-6006


From smithmc@ornl.gov Mon Jun  8 10:42:04 MDT 1998
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Reply-To: "Melissa C. Smith" 
From: "Melissa C. Smith" 
To: "'Hubert van Hecke'" 
Subject: Re: cal/raw mixup
Date: Mon, 8 Jun 1998 12:42:29 -0400
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Status: RO

what I am trying to confirm, is that you are using the bench_cal_en mode
bit?

After the 2nd you get a packet, do you ever get another  with more pulses or
do you have to reset the HM?

Melissa
>>>------;;->>  >>>---GO NOLES---;;->>  >>>------;;->>

Melissa C. Smith
Oak Ridge National Laboratory
Instrumentation & Controls Div.
P.O.B. 2008, MS-6006
Bethel Valley Road
Bldg. 3500, RM A-18
Oak Ridge, TN 37831-6006
E-mail: smithmc@ornl.gov , smithmc@utk.edu
Phone:(423) 576-0296  Fax:(423) 576-2813
http://www.ic.ornl.gov/rd-groups/msd/Personnel/smithmc.html
http://microsys6.engr.utk.edu/~smithmc/

>>>------;;->>  >>>---GO NOLES---;;->>  >>>------;;->>
-----Original Message-----
From: 'Hubert van Hecke' 
To: "Melissa C. Smith" 
Date: Monday, June 08, 1998 12:02 PM
Subject: cal/raw mixup


>yes, I need to send two pulses. After the first one, nothing happens on the
>data lines, and after the second one, a packet comes out.
>>
>> >Hi Nance,Melissa
>> >Here is the HM behavior:
>> >There seems to be interference between 'raw data mode' and bench
>> calibration
>> >mode'.
>> >If I do regular lvl1's, I get one packet in correlator mode, and 2
packets
>> in
>> >raw mode. However, in bench cal mode, I cannot make the raw mode work,
that
>> >is, except for the very first time, I get only one packet out. Moreover,
in
>> >bench cal mode with the correlator on, I need two triggers to get one
>> packet
>> >out.
>> >
>>
>> I have looked at the firmware and I don't see any relation between the
>> operation of raw mode and bench cal mode.  There must be something else
we
>> are missing.
>> When you say you need two triggers, you mean two pulses of the bench cal
>> enable right?
>>
>> Melissa
>>
>>
>---------------------------------------------------------------------
>--- Hubert van Hecke             ---      Los Alamos National Lab ---
>--- group P-25                   ---      phone: (505) 667 5384   ---
>--- email: hubert@lanl.gov       ---      fax  : (505) 665 7920   ---
>--- www home page: http://p2hp2.lanl.gov/people/hubert/home.html  ---
>---------------------------------------------------------------------


From bennett@hpmvd.lanl.gov Thu Jun 18 09:42:24 MDT 1998
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Date: Thu, 18 Jun 1998 09:42:21 -0600 (MDT)
From: Michael Bennett 
Message-Id: <199806181542.JAA12620@hpmvd.lanl.gov>
To: jaffe@p2hp6.lanl.gov, zeteta@MIT.EDU, gdsmith@lanl.gov, gxu@p2hp6.lanl.gov,
        boissevain@lanl.gov, jsimon@lanl.gov, sullivan@lanl.gov,
        marek@lanl.gov, sykim@p2hp6.lanl.gov, mjbennett@lanl.gov,
        rceja@lanl.gov, schlei@t2.lanl.gov, hubert@lanl.gov
Subject: Re: currents
Cc: shahn@lanl.gov
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Status: RO

Hello all,

	Continuing on the topic of currents through the MCM output cable--in our 
discussion yesterday there was some concern about the current-carrying 
capabilities of the wirebonds.  I just spoke with John Gunderson at ARMA designs 
on this topic.  He said that their rule of thumb is that 1 mil diameter Al wire 
over lengths of 40-60 mils could carry up to 1 amp with no problem.  The weakest 
part of the wire is where the wedge which connects to the pad is deformed to 
form the round wire, and if there is an additional stress there from 
"scrunching" the wire when bonding, it could lead to some problems; so, one 
needs to be careful to not stress the wire when bonding.  He agrees that 
multiple bonds in this case would be advisable, but overall he doesn't see a 
problem.
	
	
						Mike
						
						
************************************************************
Mike Bennett
P-25 Mail Stop H846 
Los Alamos National Laboratory
Los Alamos, NM  87545

phone:  505-665-2760
fax:    505-665-7920
email:  mjbennett@lanl.gov


From shahn@lanl.gov Thu Jun 18 17:08:30 MDT 1998
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Date: Thu, 18 Jun 1998 17:15:55 -0600
From: Sangkoo Hahn 
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To: lcope , me ,
        Jehanne Simon-Gillo ,
        Jan Boissevain , Gary Smith ,
        gary richardson , bernd schlei ,
        john sullivan , dave jaffe ,
        hubert vanhecke , larry marek ,
        guanghua xu 
Subject: Re: currents
References: <199806181542.JAA12620@hpmvd.lanl.gov>
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Status: RO

Hi, all:

This morning, with all the unknowns in current carrying capabilities of kapton cable
traces, bond-wires and MCM traces, I had done some looking into. Here is what I got.

The copper trace thickness on MCM is 4.3u by design.  (In one of the PHX-2
Mechanical Data sheet that L-M sent to Gary Richardson indicates 15u thick copper,
but our SOW says 4.3u, and Albert Sun from L-M confirmed it.)  With 4.3u, at least a
150u-wide trace is needed to have equivalent cross-section of a 1-mil copper wire.
At this point, we don't know what is the maximum allowable current-carrying
capability of 1-mil copper wire, either. Lock-Mart is using 15u copper for their
high-power circuits. I am trying to contact Lock-Mart  to find out what the
implications are if we choose to use 15u process. In the mean time, I am also
working with Gary to increase the trace widths on the MCM.

Concerning the bond-wires: I did some quick tests on Al and Au bond-wires to confirm
the "rule-of-thumb" 1A current. I found 1.5-mil Al and 1-mil Au wires in the lab and
hooked it up to a current-limited supply. The 1.5-mil Al wire tests were
inconclusive as the electrode has to break through the thin oxide layer, damaging
the wires in the process. However, at about 2.5mm (100-mil) wire lengths, the wire
seem to evaporate at or above 0.75A. Of course, this test is not quite realistic;
the electrodes touching the wire work as a good heat-sink, thus cooling the
bond-wire better than the kapton and MCM bond pads could.

The 1-mil Au tests gave more consistent results. In essence, the current increased
with decreasing wire lengths, which is reasonable considering the heat-sinking
effect of the electrodes. Again, the heat-sinking can not be so good in reality.

The wire lengths used and corresponding fusing currents are:

    2.5mm           ~800mA @  ~0.3V across the wire
    5mm              ~700mA @  ~0.3V
    12.5mm        ~550mA @ ~1.0V
    25mm            ~500mA @ ~1.5V

There is about 3 ohms/inch of resistant developing across the wire before the wire
fuses.

With the conductivity of the Au better than Al by approx. 20%, the fusing current of
Al would be less by about that much. I also looked up a reference book, which shows
the fusing current of a 40 AWG (3.1-mil diameter) Al wire at 1.31A.  If we can
extrapolate the fusing current, 1.5-mil Al wire has fusing current of 310 mA when
there is no heat sinking, which we may use as the upper boundary of the current
limit. (1.5-mil Al wire is not a standard wire size but most vendors should still be
able to handle it.)

>From the fact that the bond-joint, not the wire itself, is the weakest link of the
current carrying capability, the maximum current per bond wire should be less than
340 mA.  We also has to worry about the long-term integrity of the bond joints due
to the electro-migration caused by passing too much currents through it . On the
other hand, the industry-standard maximum recommended current (extrapolated from a
table for standard cables) for a 1.5-mil wire is about 8 mA. Since the bond-wire is
quite short, not a normal application of wires, I feel that the usable current could
be much higher without incurring reliability issue. So, I would put the maximum
current for a 1.5-mil Al wire somewhere between 8 mA and 340mA.

If I have to choose a number, 50mA (at about the geometric mean) maybe a pretty good
guess for me. It means we need minimum of two bond wires for all the current
carrying pads even after we rearrange the pin-assignments as Hubert's email informed
you earlier.

The kapton cable traces have enough current capability so long as we use 1-Oz copper
and 10-mil or greater trace widths.

I am also looking into the possibility of using different means of attaching the MCM
output cable to the MCM. Is it possible, or even preferrable, to use a connector on
the MCM side as well? Connectors may also improve on mechanical integrity of the
joints as well. Can we use a TAB-bonding, instead? No clear answer yet, but
possibilities.


Sangkoo
7-2507




From shahn@lanl.gov Wed Jun 24 09:52:12 MDT 1998
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Date: Wed, 24 Jun 1998 09:59:59 -0600
From: Sangkoo Hahn 
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To: lcope , me ,
        Jehanne Simon-Gillo ,
        Jan Boissevain , Gary Smith ,
        gary richardson , bernd schlei ,
        john sullivan , dave jaffe ,
        hubert vanhecke , larry marek ,
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Subject: MCM power traces
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Status: RO

Hi, all:

Here's what we are doing to mitigate the MCM trace width
problems on power supply lines.

Lockheed-Martin, after all, didn't have any recommended
currents vs. trace lenths and widths on MCM, so I had to set
up my own criteria. Calculation shows that, for a copper
trace that is 4.5u thick (for the standard process,) the
trace resistance is ~4 Ohms per mm length for 1u trace
width. (A 100u wide trace results in 0.04 Ohms for every
mm.) To limit the total resistance from the output connector
pad to any on-board chip to within 0.5 Ohm total, the
following standard trace widths were set:

    Trace lengths                            Minimum trace
width

        <1mm                                    250u
        1 - 2 mm                                375u
         >2mm                                   500u

The maximum single line trace length on the MCM is about
40mm, which results in ~0.32 Ohms. For a 100mA current, the
voltage drop along the trace is 32mV, which is comfortably
small.

There is also a significant fringe benefit for having wider
traces on the power and ground lines; better shielding and
decoupling.

According to Frank Cappo, L-M, a standard via can handle
~400mA, but we are putting in a generous number of vias (and
at least two vias when squeezed) for any power and ground
lines.

I sat down with Gary Richardson yesterday afternoon, and
went through individual power lines as well as ground traces
to see the feasibility of widening the traces and adding
more via holes.  (By the way, there were enough trace widths
on some of the power lines and ground returns but not all,
especially the comparator supply line.)
There are three different analog power lines, AVDD_PRE,
AVDD1 and AVDD_CMP, and one digital, DVCC.  There also are
three different grounds, AGND1 (a combined return for
AVDD_PRE and AVDD1), AGND_CMP and DGND. After trying to do
real-time layout work together, we finally agreed to have
Gary complete the changes first based on the above
guidelines, and we go over the traces again later.


Regards,


Sangkoo
7-2507




From jsimon@p2hp2.lanl.gov Thu Jun 25 10:40:38 MDT 1998
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From: "'Jehanne Simon-Gillo'" 
Message-Id: <199806251640.KAA13177@p2hp2.lanl.gov>
Subject: summary of request (fwd)
To: shahn@lanl.gov, hubert@lanl.gov
Date: Thu, 25 Jun 1998 10:40:37 MDT
X-Mailer: Elm [revision: 212.2]
Status: RO

Dear Sangkoo and Hubert,

I have been having several discussions with Chi et al and here
is a somwhat detailed list of measurements which Chi 
"strongly" encourage us to perform on the PC MCM immediately.
As Chi is not an MCM expert, he acknowledges that some of these
requests may not be good ones, but then we should thoroughly explain why.
These measurements should take a high priority in your MCM tests and we
will need to document them with our other MCM tests and circulate to the
general public. I will discuss them with you in more detail on Monday,
but I wanted to give you the opportunity to start on those that you could.

Best regards,
Jehanne

> 
> Dear Jehanne:
> 	This is the list things I think one could measure and checkout about
> MVD MCM PCB prototype board.
> 	(1) Fire random trigger for 20K events, one should get average
> 20K/64 events per AMU cell. One then could plot average ped. value vs cell
> number. sigma(ped) vs cell number for all channel. For this you have to turn
> correlator off. Sigma on the ped. should be reasonable small. 
> 	(2) Send in calibration pulse and do the same thing. Now one could
> plot ADC value vs calibration pulse DAC value (??). If one remove the
> ped. Dependence vs the cell number. The calibration result should be 
> Independent of the cell number.
> 	(3) repeat above process with 5 trigger in a row that at least 400
> ns apart but less then 10 microsec between triggers. Repeat items 1 and 2.
> Hopefully the noise introduced by this should be much less then charge value
> associate with 1 mips particle.
> 	(4) Turn on the correlator, run 20K events on some configuration and
> make sure it make sense. 
> 
> 	The list below is questions I have:
> 
> 	(1) How full is the FPGA for heap manager and data formatter.
> 	(2) Before FPGA boot up, is all pin tri-stated ??
> 	(3) If one use current limiting resistor, what is the voltage in the
> analog powerline before FPGA is full booted. Is there extra current flow
> between digital and analog power supply.
> 	(4) run system at 25KHz trigger rate, what is the current drawn in
> the system vs no trigger. In here one just dump the data on the floor...
> 
> 
> 
>  
> 							Best Regards,
> 
> 
> 							Chi
> 
> 


From shahn@lanl.gov Fri Jun 26 12:03:09 MDT 1998
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From: Sangkoo Hahn 
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To: "'Hubert van Hecke'" 
Subject: Re: help!
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Hubert:

While I was checking different lines, I noticed the sr_latch (sr_dclk)
activating frequently, almost like sr_datain  line. Did you see it before? It
is counter to what I would expect. The sr_dout (the done-line) has irregular
waveform occurring too often as well.

Sangkoo

-------------------------------------

'Hubert van Hecke' wrote:

> Not really. I don't think I've seen a situation where the xilinx refuses to
> load. Is +5 digital on?                        Hubert
> >
> > Hubert:
> >
> > I finally got back on the bench to turn on the PC_MCM, and
> > couldn't get past loading the xilinx. The analog current
> > stays high at ~300ma. Checked the serial data and clock,
> > which were good. Any suggestions?
> >
> > Sangkoo
> >
> >
> >
>
> --
> ---------------------------------------------------------------------
> --- Hubert van Hecke             ---      Los Alamos National Lab ---
> --- group P-25                   ---      phone: (505) 667 5384   ---
> --- email: hubert@lanl.gov       ---      fax  : (505) 665 7920   ---
> --- www home page: http://p2hp2.lanl.gov/people/hubert/home.html  ---
> ---------------------------------------------------------------------




From shahn@lanl.gov Tue Jun 30 14:46:05 MDT 1998
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Date: Tue, 30 Jun 1998 14:54:12 -0600
From: Sangkoo Hahn 
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MIME-Version: 1.0
To: Chuck Britton 
CC: ericson@icsun1.IC.ORNL.GOV, Jehanne Simon-Gillo ,
        hubert vanhecke , Jan Boissevain 
Subject: Re: MCM signal lines
References: <199806301414.KAA04133@icsun1.IC.ORNL.GOV>
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Status: RO
X-Status: 

Chuck:

It is better to implement the changes in the MCM as we are going
through the layout for the final time. We can implement the changes
now without impacting the Power-Comm board which was produced already
and is ready for testing. It is best for you to send us a new
schematic reflecting the said changes (and the following.)

I have been testing the pull-down resistors for the "AZ" and "CMP-RST"
inputs to reduce the amount of turn-on current before the Xilinxs are
configured. 22k resistors on both locations bring the current down to
~100mA total for all the analog lines. Without the resistors, it stays
at ~300mA. (There are only 3 pairs of TGV and AMUADC.)

The current increases almost abruptly beyond 22k, so I'd like to use a
15k (~30% below 22k) as the pull down resistor values to have some
margin. There may be some software fixes that may or may not be
fool-proof, but this hardware fix will cure the problem forever. The
Xilinx databook says 1mA as sourcing current for the I/O blocks, so I
don't see any problem driving 15k, which takes only ~0.35mA for 5V
swing, or 1/3 of a nominal capability. What's your opinion?

Regards,


Sangkoo

-------------------------------------------

Chuck Britton wrote:

> Sangkoo,
> We will correct the schematic at the connector level.
> The input connector will now have
>
> pin 19 -> readback enable
> pin 20 -> serial enable
>
> Is this OK?
>
> At 12:09 PM 6/26/98 -0600, you wrote:
> >Hi, all:
> >
> >While testing the PC version of the MCM, I noticed the
> >following discrepancy in interconnections. This is the only
> >interconnection problem I ran into so far.
> >
> >    50-pin     Signal Assignmt         Bus Name
> >HM Chip Pad-#        Name
> >
> >       p-19    serial enable
> >SR_CON3                pad-3                 sr_rdbk
> >       p-20    read back enable
> >SR_CON2                pad-171             sr_rst
> >
> >It appears that the two pins are swapped by attaching wrong
> >"text" labels of the two lines in a bus. This problem may be
> >solved by reprogramming the Xilinx, but it is better to
> >remove any future confusion by correcting the
> >interconnections now.
> >
> >Another topic: Recently, Chi at Columbia sent this to
> >Jehanne, and I am copying it to you for your thoughts,
> >especially on the questions towards the bottom. We will have
> >further discussions on this later.
> >
> >
> >Regards,
> >
> >Sangkoo
> >
> >---------------------------------------- Chi's message below
> >------------------------
> >
> >This is the list of things I think one could measure and
> >checkout about
> > MVD MCM PCB prototype board.
> >
> >        (1) Fire random trigger for 20K events, one should
> >get average
> >  20K/64 events per AMU cell. One then could plot average
> >ped. value vs cell
> >  number. sigma(ped) vs cell number for all channel. For
> >this you have to turn
> >  correlator off. Sigma on the ped. should be reasonably
> >small.
> >
> >        (2) Send in calibration pulse and do the same thing.
> >Now one could
> >  plot ADC value vs calibration pulse DAC value (??). If one
> >remove the
> >  ped. Dependence vs the cell number. The calibration result
> >should be
> >  Independent of the cell number.
> >
> >        (3) repeat above process with 5 trigger in a row
> >that at least 400
> >  ns apart but less then 10 microsec between triggers.
> >Repeat items 1 and 2.
> >  Hopefully the noise introduced by this should be much less
> >then charge value
> >  associate with 1 mips particle.
> >
> >        (4) Turn on the correlator, run 20K events on some
> >configuration and
> >  make sure it make sense.
> >
> >        The list below is questions I have:
> >
> >        (1) How full is the FPGA for heap manager and data
> >formatter?
> >        (2) Before FPGA boot up, are all pins tri-stated ?
> >        (3) If one use current limiting resistor, what is
> >the voltage in the
> >  analog powerline before FPGA is fully booted? Is there
> >extra current flow
> >  between digital and analog power supplies?
> >        (4) If system is at 25KHz trigger rate, what is the
> >current drawn in
> >  the system vs no trigger? In here, one just dump the data
> >on the floor?
> >
> >---------------------- End of Chi's message
> >-------------------
> >
>
> C. L. Britton, Ph.D.
> Oak Ridge National Laboratory
> P. O. Box 2008  MS6006
> Oak Ridge, TN 37831-6006
> _________________________
> email:  brittoncl@ornl.gov
> Phone: (423) 574-1878
> FAX:    (423) 576-2813
> WWW: http://www.ic.ornl.gov/rd-groups/msd/Personnel/brittoncl.html




From sullivan Tue Jun 30 17:44:49 MDT 1998
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From: John Sullivan 
Message-Id: <199806302344.RAA02411@p2hp4.lanl.gov>
Subject: Re: do you know...
To: hubert (Hubert van Hecke)
Date: Tue, 30 Jun 1998 17:44:48 MDT
Cc: sullivan
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Hi Hubert,
  After I contacted you I found some (potentially outdated, but plausible)
documentation on this is a report Nance put on the web:
http://p2hp2.lanl.gov/phenix/mvd/notes/1998/PHENIX-MVD-98-14/dcimdoc.html

  I find that the format described is almost identical to the
format the drift chamber people have assumed in setting up their
staf tables, so it seems like a very good start and that's what I
am assuming for now. There are some details I do not understand
precisely (e.g. part of the description of parity error handling
is uncllear about which of the words is used to contain the
resulting error information.)

Thanks,
John

From ericsonmn@ornl.gov Wed Jul  1 13:35:04 MDT 1998
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Date: Wed, 01 Jul 1998 15:32:24 -0400
To: "'Hubert van Hecke'" 
From: ericsonmn@ornl.gov (Nance Ericson)
Subject: Re: fpga
Cc: jsimon@lanl.gov, britton@icsun1.IC.ORNL.GOV, ericson@icsun1.IC.ORNL.GOV,
        smithmc@icsun1.IC.ORNL.GOV
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Hubert,

The fpga programming software we are currently using was developed
using Labview.  This code will not be readable except with Labview
software.  I can ftp the files to you but they will be useless 
unless you have the labview software package.

The original beam test PC software is on the PC in the lab and I 
could send it to you but cannot guarantee that it even works.  There
are several versions on the PC.

Regards,

Nance


At 10:04 AM 6/30/98 -0600, you wrote:
>Hi Melissa, Nance,
>I recall that some of the fpga programming is in a form that reads much
like a 
>C program. Could you send us a copy of those parts? Also, the other parts
are 
>ineresting also. If you send them too, we can see if we can read them on one 
>of the engineer's stations here. 
>
>The specific question is this: The serial data out line (pad 11) is used 
>during the download phase to indicate the 'done' status of both fpga's. 
>We have an led hooked up to it, and I recall that long ago we used to see
the 
>led change state at the completion of a download. We don't see that any more 
>(actually this was already the case when we were in ornl, but we glossed
over 
>it). What we see on the scope is that the line goes high and then low again
>very fast (<100ns). Is that programmed to do that now, or should we worry 
>about that?                              Hubert, Sangkoo, Bernd
>--
>---------------------------------------------------------------------
>--- Hubert van Hecke             ---      Los Alamos National Lab ---
>--- group P-25                   ---      phone: (505) 667 5384   ---
>--- email: hubert@lanl.gov       ---      fax  : (505) 665 7920   ---
>--- www home page: http://p2hp2.lanl.gov/people/hubert/home.html  ---
>---------------------------------------------------------------------
>

From owner-phenix-mvd-l@bnl.gov Tue Jul  7 13:50:51 MDT 1998
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From: "'Hubert van Hecke'" 
To: phenix-mvd-l@bnl.gov
Subject: mcm fpga problems
X-Mailer: Elm [revision: 212.2]
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Status: RO

Hi Gang,

Here is a list of MCM/fpga problems that we have seen, listed in no particular
order:

1) Start bit. This is a pattern of 4 ticks on the data out A line, while the
   clock is high. I looked at this pattrn for many triggers (trigger rate
   about 2Hz). After 100-200 triggers, sometimes the picture changes to where 
   the 4th data line pulse does not go down till the next clock pulse.
   I can make the pattern go back to normal in at least two ways: by clicking 
   100-200 more triggers, or by issuing a integrator reset mode pulse.
2) In the writeup on the DCMIM, the data words are supposed to be 10 bits, yet 
   the current fpga puts out 11-bit words. 
3) Recently, the digital +5 current has gone up by a factor of 3, and the HM 
   is hotter than it used to be. We are not sure if this is correlated with 
   the installation of the 15K pull-down resistors on the amuadc.
4) sometimes the data out clock, which is supposed to be active only during 
   the shipping of a data packet, is found running.
5) During fpga downloading, sometimes the 'done line' is fluttering high and 
   low. Sometimes not.
6) There is interference between the bench cal mode, cal enable serial string 
   bit, raw/correlator string bit and the lvl-1 trigger.
   For example, after enabling the cal, and using the bench cal or phenix cal
   mode, one can never get the lvl1 trigger mode to work again.
   There are several combinations where the raw mode bit no longer works (only
   one data packet comes out)
7) Last thursday, we tied the adc data out bus lines to +5 and 0 via 15K 
   resistors. The HM started producing 9,10,11 bit words, where before that it
   only produced 11-bit words.

Here are some questions from Chi:
>       (1) How full is the FPGA for heap manager and data formatter.
>       (2) Before FPGA boot up, is all pin tri-stated ??                  
>       (3) If one use current limiting resistor, what is the voltage in the
>           analog powerline before FPGA is full booted. Is there extra
>           current flow between digital and analog power supply.                                  

                                           Hubert, Sangkoo, Bernd.

--
---------------------------------------------------------------------
--- Hubert van Hecke             ---      Los Alamos National Lab ---
--- group P-25                   ---      phone: (505) 667 5384   ---
--- email: hubert@lanl.gov       ---      fax  : (505) 665 7920   ---
--- www home page: http://p2hp2.lanl.gov/people/hubert/home.html  ---
---------------------------------------------------------------------

From smithmc@ornl.gov Wed Jul  8 06:59:12 MDT 1998
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Reply-To: "Melissa C. Smith" 
From: "Melissa C. Smith" 
To: "'Hubert van Hecke'" , 
Cc: , , 
Subject: Re: tests
Date: Wed, 8 Jul 1998 08:58:37 -0400
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Status: RO

>Hi Nance,
>1) the digital current did not go down when we disconnected the pulldown
>resistors from the amuadc.

I suspect there may be an I/O contention problem resulting from an incorrect
pad assignment on the FPGA.  I will double check this before I run another
implementation on the FPGA.



>3) now, even after a clean download, we never see two data packets any
more.
>

Could you please expand on this...  Does this mean only the 2nd level 1
doesn't work???  or Does the raw data packet never work???



Also, Nance said that your were planning to send some detailed examples of
the mode control problems that you have experienced.  I will need these
before I can begin to debug....

Thanks,

Melissa and Nance

 
 

 ps version

  
 

 ps version
 

 
 

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