| US 7,355,254 B2 | ||
| Pinning layer for low resistivity N-type source drain ohmic contacts | ||
| Suman Datta, Beaverton, Oreg. (US); Jack T. Kavalieros, Portland, Oreg. (US); Robert S. Chau, Beaverton, Oreg. (US); and Mark L. Doczy, Beaverton, Oreg. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Jun. 30, 2006, as Appl. No. 11/480,667. | ||
| Prior Publication US 2008/0017891 A1, Jan. 24, 2008 | ||
| Int. Cl. H01L 29/76 (2006.01); H01L 21/8238 (2006.01) | ||
| U.S. Cl. 257—382 [257/E29.145; 438/233; 438/586; 438/607] | 18 Claims |
| 1. An apparatus comprising:
an N-type transistor structure including a gate electrode formed on a substrate and a source region and a drain region formed
in the substrate;
a contact to the source region; and
a pinning layer disposed between the source region and the contact and defining an interface between the pinning layer and
the source region,
wherein the pinning layer comprises indium nitride or an indium-group III-nitride having donor-type surface states in a conduction
band.
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