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ALSNews           Vol. 67           December 11, 1996

Table of Contents


    1. OPERATIONS UPDATE
    2. SPECTROMICROSCOPY USED TO ADDRESS INTEGRATED CIRCUIT CHALLENGES
    3. HOW DID INTEGRATED CIRCUITS GET SO COMPLICATED?
    4. ALS PARKING POLICY SHIFTS GEARS
    5. ALSNEWS AND BERKELEY LAB ON HOLIDAY

1. OPERATIONS UPDATE
(contact: rmmiller@lbl.gov)

Beam reliability for the last two weeks was 90.4% overall and 88.1% for user shifts. All outages were of short duration. The user-shift average for the last two weeks reflects the "camshaft" mode of operation in which 304 buckets are filled to approximately 1 mA/bucket, and then 20 mA is stacked in bucket 304. This operation adds several minutes to each fill compared to the time required to fill and ramp for normal 1.9-GeV operation.

Operations Summary for December 11 - January 13

Dec 11, 00:00- Dec 16, 07:15  1.5-GeV/400-mA/304-bunch user operations
Dec 16, 07:30-24:00           Maintenance & startup
Dec 17, 00:00-24:00           Accelerator physics
Dec 18, 00:00-08:00           User scrubbing & special operations
                              (1.1-GeV/400-mA/304-bunch user operations)
Dec 18, 08:00- Dec 23, 23:15  1.5-GeV/400-mA/304-bunch user operations
Dec 24, 00:00- Jan 06, 07:30  No operations - holidays
Jan 06, 07:30-24:00           Maintenance & startup
Jan 07, 00:00-24:00           Accelerator physics
Jan 08, 00:00-08:00           User scrubbing & special operations
Jan 08, 08:00- Jan 13, 07:15  1.9-GeV/300-mA/304-bunch user operations

2. SPECTROMICROSCOPY USED TO ADDRESS INTEGRATED CIRCUIT CHALLENGES
(contact: singh@xraylith.wisc.edu)

As manufacturers reduce the size of integrated circuit (IC) components to fit more components on each IC chip, there is more going on than a simple reduction in scale. Confinement in ever-smaller spaces can affect the properties of IC component materials in unexpected, and sometimes problematic, ways. A research group working at the ALS and at Stanford Synchrotron Radiation Laboratory (SSRL) has used spectromicroscopy to characterize these changes, laying the groundwork for improvements in the miniaturization process.

Among the shrinking components of ICs are vias, the vertical electrical connections joining layers in an integrated circuit. Via construction involves a complex series of layers to produce the desired physical and electrical characteristics (see item 3 below). One of these layers is titanium silicide (TiSi2), which improves the electrical contact between a silicon substrate and the rest of the via above it. To produce the TiSi2 layer, manufacturers first deposit a blanket layer of titanium on a substrate patterned in polycrystalline silicon (poly-Si) and silicon dioxide (SiO2), with poly-Si where the silicide layer is desired. Then a formation anneal (typically heating to 700 degrees C for a 30-nm Ti layer) helps the titanium react with Si atoms from the poly-Si to form TiSi2, which exists at this stage in a phase called C49. A selective wet etch removes the titanium that has not reacted with Si, and finally a conversion anneal (typically 900 degrees C) transforms the TiSi2 into a lower-resistivity phase known as C54.

This process is susceptible to problems when lines on the IC are below a micron in width, because of several phenomena. First, during the formation anneal, the silicide grows laterally a little outside the lines of the poly-Si pattern. This is because outlying titanium atoms attract silicon atoms from the poly-Si and from the newly formed TiSi2 lying over the poly-Si, causing the silicon atoms to migrate laterally. This leaves a titanium-rich band of silicide at the edge of the poly-Si pattern. The selective wet etch removes this titanium-rich material, leaving a TiSi2 C49 line narrower than the original poly-Si line (linewidth narrowing). Second, when linewidths are less than a micron, by design or because of linewidth narrowing, the conversion anneal can cause the TiSi2 to agglomerate, causing circuit malfunctions by breaking the circuit pattern and interrupting the conversion of C49 to C54.

A research group led by Sangeet Singh (University of Wisconsin-Madison) used spectromicroscopy to examine these problems in IBM static random access memory (SRAM) chips. They found unexpected local variations in lateral silicide growth (see their data here for details), further complicating models of what was going on. In order to simplify their model by addressing one phenomenon at a time, they decided to study a simpler case of silicide growth. Using electron-beam lithography, they produced a test pattern of titanium on clean silicon (111) in the shape of spokes, each spoke narrowing from 5 microns at the outer edge to 0.1 micron at the inner tip. Only after the unwanted titanium was removed did they anneal the sample to produce TiSi2. Thus, silicide growth in this sample was one-dimensional (up away from the silicon substrate), rather than both one-dimensional (up) and two-dimensional (lateral) as in the SRAM samples.

The group examined the spoke pattern with two x-ray photoemission spectromicroscopes providing complementary information on Ti and Si absorption edges: MAXIMUM (scanning, 130 eV photon energy, Si 2p and Ti 3p edges), used at ALS Beamline 6.3.2; and PRISM (full-field imaging, Ti 2p edge), used at SSRL. They found differences in spectral line shape between the spokes' tips, edges, and centers, indicating different types of bonding in these areas. This is consistent with differences in phase in the spoke pattern, since the atoms in the C49 and C54 phases of TiSi2 have different nearest-neighbor configurations and thus should have different electronic structures. This may mean that in the very narrow tips and along the edges, spatial confinement inhibits the conversion of C49 to C54, so that the spokes remain bordered in C49 even after the conversion anneal. Verification of this explanation using photoemission spectromicroscopy would require that reference samples of C49 and C54 be positively identified using diffraction and then characterized using photoemission and photoabsorption spectroscopy. Researchers also examined the spoke pattern with an atomic force microscope, noting differences in microstructure (possibly different grain sizes) at the spoke edges and tips which suggested that the TiSi2 there could be C49. Future high-resolution studies are planned using MAXIMUM on ALS undulator beamline 12.0 to continue the study of TiSi2 formation on specially designed microstructures. Additional PRISM measurements of the Si 2p edge are also planned, as are the experiments mentioned above on C49 and C54 reference samples. These spectromicroscopic studies may suggest refinements to the siliciding process that will make manufacture of future generations of ICs more accessible.

Principal investigators for this research: TiSi2 experiments: Sangeet Singh (University of Wisconsin at Madison; advisor--Franco Cerrina, PI for MAXIMUM) PRISM (used at SSRL): Jo Stohr (IBM Almaden Research Center) For more information: singh@xraylith.wisc.edu http://www.xraylith.wisc.edu/info/maximum/MAXIMUM.html

3. HOW DID INTEGRATED CIRCUITS GET SO COMPLICATED?

The complex structures used in the current generation of integrated circuits (ICs), and the challenges now being addressed in their miniaturization, are partly the product of changes made as IC feature sizes were reduced below one micron. Before this scale transition, aluminum was generally used as the metal conductor in ICs. Contacts (known as vias) between the aluminum and the underlying silicon substrate were made by creating tapered wells in the material separating them and depositing aluminum by physical vapor deposition on the floor and walls of these wells, so that the aluminum was in direct contact with the silicon. However, as the scale of this scheme decreased, these tapered vias took up too much space and the diffusion of aluminum into the silicon substrate began causing voltage spikes at IC junctions. Therefore, IC manufacturers began using a new kind of via produced by making vertical-walled holes in the separating material and filling them with tungsten by chemical vapor deposition. Tungsten shared aluminum's tendency to diffuse into the surrounding material, so a thin diffusion barrier such as titanium nitride (TiN) was deposited into the well first. The electrical contact between tungsten and silicon, or between TiN and silicon, was poor, so a titanium silicide (TiSi2) layer between the silicon substrate and the TiN layer was added. This combination served well, with good electrical contact and adhesion among the layers and less interdiffusion.

The quality of the TiSi2 layer is important to this scheme. TiSi2 can exist in two phases, known as C49 and C54. In the manufacturing process, the higher-resistivity phase C49 (60-90 microohms-cm) forms first. It is transformed by a high-temperature annealing process to its C54 phase, with resistivity several times lower (12-15 microohms-cm). Researchers have noticed that this transformation can be inhibited, giving higher final resistivities, when IC feature sizes are below one micron. (See item 2 above for further details on the IC manufacturing process and on an experiment exploring TiSi2 formation.)

4. ALS PARKING POLICY SHIFTS GEARS

The ALS has worked out a new reserved-parking policy in cooperation with spokespersons from beamline participating research teams (PRTs). The spaces on the east side of the ALS building will now be available for reservations on an as-needed basis. A user may request a parking space for a limited time (six weeks maximum) while setting up or performing an experiment at the ALS. Parking spaces will be allocated as available, with attention to fairness to all ALS users. Thus, users from a given PRT or research group can request more than one parking space for the duration needed, rather than having one assigned whether needed or not (as was the case for undulator beamlines under the previous policy).

Users should give their reservation requests to Joan Minton by phone (510-486-4067) or email (jpminton@lbl.gov) and may make their requests in advance of their visits. Joan will also continue to reserve spaces on the north side of the ALS on a day-to-day basis for infrequent visitors.

5. ALSNEWS AND BERKELEY LAB ON HOLIDAY

Everyone at Berkeley Lab, including the ALSNews editors, will take a much-needed break for the holidays. The Lab will shut down on the evening of December 23 and reopen on the morning of January 2. ALS user operations will resume on January 8, and the next issue of ALSNews is due to be delivered on the same day. We wish you all a pleasant and relaxing holiday season.